RISC-V
E37329
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
Aliases (4)
Statements (78)
| Predicate | Object |
|---|---|
| instanceOf |
instruction set architecture
→
open standard → reduced instruction set computing architecture → |
| allows |
custom extensions
→
proprietary extensions → |
| basedOn |
RISC principles
→
|
| competesWith |
ARM architecture
→
MIPS architecture → x86 architecture → |
| countryOfOrigin |
United States
→
|
| designedFor |
embedded systems
→
general-purpose computing → research → |
| developedBy |
UC Berkeley ASPIRE Lab
→
UC Berkeley Parallel Computing Laboratory → |
| governedBy |
RISC-V International
→
|
| hasBaseISA |
RV128I
→
RV32I → RV64I → |
| hasBinaryFormat |
ELF
→
|
| hasDebugSupport |
OpenOCD for RISC-V
→
|
| hasDesignGoal |
energy efficiency
→
long-term stability of base ISA → scalability → simplicity → |
| hasEcosystem |
open-source hardware implementations
→
open-source software toolchains → |
| hasEndianness |
little-endian (primary)
→
|
| hasExtension |
A (atomic instructions)
→
B (bit-manipulation extension) → C (compressed instructions) → D (double-precision floating point) → F (single-precision floating point) → H (hypervisor extension) → K (cryptography extensions) → M (integer multiplication and division) → P (packed-SIMD extension) → V (vector extension) → Zicsr (control and status register instructions) → Zifencei (instruction-fetch fence) → |
| hasLicenseModel |
open and non-restrictive license
→
|
| hasProperty |
extensible
→
free to use → modular → open → royalty-free → |
| hasSimulator |
QEMU RISC-V target
→
Spike RISC-V ISA simulator → |
| hasSpecification |
debug specification
→
privileged architecture specification → unprivileged ISA specification → vector extension specification → |
| hasToolchain |
GCC for RISC-V
→
LLVM/Clang for RISC-V → |
| inspiredBy |
Berkeley RISC projects
→
MIPS architecture → SPARC → |
| originatedAt |
University of California, Berkeley
→
|
| previouslyGovernedBy |
RISC-V Foundation
→
|
| supportsAddressWidth |
128-bit
→
32-bit → 64-bit → |
| supportsOperatingSystem |
FreeBSD
→
Linux → NetBSD → OpenBSD → RT-Thread → Zephyr RTOS → |
| supportsPrivilegeLevel |
hypervisor mode (H)
→
machine mode (M) → supervisor mode (S) → user mode (U) → |
| usedIn |
IoT devices
→
Linux-capable processors → accelerators → edge computing devices → microcontrollers → system-on-chips → |
Referenced by (15)
| Subject (surface form when different) | Predicate |
|---|---|
|
GDB
→
GNU C Library → GNU Compiler Collection → GNU Debugger → LLVM → Linux → |
supportsArchitecture |
|
RISC-V
("RV32I")
→
RISC-V ("RV64I") → |
hasBaseISA |
|
Gentoo Linux
→
OpenWrt → |
supportsPlatform |
|
FreeBSD
→
|
architectureSupport |
|
RISC-V
("Zifencei (instruction-fetch fence)")
→
|
hasExtension |
|
MIPS
→
|
influenced |
|
Clang
→
|
targetArchitecture |
|
MicroPython
("RISC-V microcontrollers")
→
|
targetPlatform |