RISC-V

E37329

instruction set architecture open standard reduced instruction set computing architecture

RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.

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All labels observed (23)

Label	Occurrences
RISC-V canonical	29
RISC-V architecture	5
RISC-V instruction set architecture	5
RISC-V ISA	2
RISC-V base integer ISA	2
RV32I	2
RV64I	2
RISC-V 128-bit integer ISA	1
RISC-V 64-bit integer ISA	1
RISC-V C compressed extension	1
RISC-V I base integer extension	1
RISC-V ISA specification	1
RISC-V ISA specifications	1
RISC-V SoCs	1
RISC-V base and standard extensions	1
RISC-V base integer ISA RV128I	1
RISC-V base integer ISA RV32I	1
RISC-V base integer extension I	1
RISC-V floating-point extensions	1
RISC-V microcontrollers	1
RISC-V modular extension scheme	1
RISC-V privileged architecture specifications	1
Zifencei (instruction-fetch fence)	1

Statements (78)

Predicate	Object
instanceOf	instruction set architecture ⓘ open standard ⓘ reduced instruction set computing architecture ⓘ
allows	custom extensions ⓘ proprietary extensions ⓘ
basedOn	RISC principles ⓘ
competesWith	Acorn RISC Machine ⓘ surface form: ARM architecture MIPS ⓘ surface form: MIPS architecture x86 ⓘ surface form: x86 architecture
countryOfOrigin	United States of America ⓘ surface form: United States
designedFor	embedded systems ⓘ general-purpose computing ⓘ research ⓘ
developedBy	UC Berkeley ASPIRE Lab ⓘ UC Berkeley Parallel Computing Laboratory ⓘ
governedBy	RISC-V International ⓘ
hasBaseISA	RV128I ⓘ RISC-V self-linksurface differs ⓘ surface form: RV32I RISC-V self-linksurface differs ⓘ surface form: RV64I
hasBinaryFormat	ELF ⓘ
hasDebugSupport	OpenOCD for RISC-V ⓘ
hasDesignGoal	energy efficiency ⓘ long-term stability of base ISA ⓘ scalability ⓘ simplicity ⓘ
hasEcosystem	open-source hardware implementations ⓘ open-source software toolchains ⓘ
hasEndianness	little-endian (primary) ⓘ
hasExtension	A (atomic instructions) ⓘ B (bit-manipulation extension) ⓘ C (compressed instructions) ⓘ D (double-precision floating point) ⓘ F (single-precision floating point) ⓘ H (hypervisor extension) ⓘ K (cryptography extensions) ⓘ M (integer multiplication and division) ⓘ P (packed-SIMD extension) ⓘ V (vector extension) ⓘ Zicsr (control and status register instructions) ⓘ RISC-V self-linksurface differs ⓘ surface form: Zifencei (instruction-fetch fence)
hasLicenseModel	open and non-restrictive license ⓘ
hasProperty	extensible ⓘ free to use ⓘ modular ⓘ open ⓘ royalty-free ⓘ
hasSimulator	QEMU RISC-V target ⓘ Spike RISC-V ISA simulator ⓘ
hasSpecification	debug specification ⓘ privileged architecture specification ⓘ unprivileged ISA specification ⓘ vector extension specification ⓘ
hasToolchain	GNU Compiler Collection ⓘ surface form: GCC for RISC-V LLVM ⓘ surface form: LLVM/Clang for RISC-V
inspiredBy	Berkeley RISC projects ⓘ MIPS ⓘ surface form: MIPS architecture SPARC microprocessor architecture ⓘ surface form: SPARC
originatedAt	University of California, Berkeley ⓘ
previouslyGovernedBy	RISC-V International ⓘ surface form: RISC-V Foundation
supportsAddressWidth	128-bit ⓘ 32-bit ⓘ 64-bit ⓘ
supportsOperatingSystem	FreeBSD ⓘ Linux ⓘ NetBSD ⓘ OpenBSD ⓘ RT-Thread ⓘ Zephyr RTOS ⓘ
supportsPrivilegeLevel	hypervisor mode (H) ⓘ machine mode (M) ⓘ supervisor mode (S) ⓘ user mode (U) ⓘ
usedIn	IoT devices ⓘ Linux-capable processors ⓘ accelerators ⓘ edge computing devices ⓘ microcontrollers ⓘ system-on-chips ⓘ

Referenced by (63)

Full triples — surface form annotated when it differs from this entity's canonical label.

Linux → supportsArchitecture → RISC-V ⓘ

GNU Compiler Collection → supportsArchitecture → RISC-V ⓘ

GNU Debugger → supportsArchitecture → RISC-V ⓘ

MicroPython → targetPlatform → RISC-V ⓘ

this entity surface form: RISC-V microcontrollers

RISC-V → hasBaseISA → RISC-V self-linksurface differs ⓘ

this entity surface form: RV32I

RISC-V → hasBaseISA → RISC-V self-linksurface differs ⓘ

this entity surface form: RV64I

RISC-V → hasExtension → RISC-V self-linksurface differs ⓘ

this entity surface form: Zifencei (instruction-fetch fence)

MIPS → influenced → RISC-V ⓘ

Gentoo Linux → supportsPlatform → RISC-V ⓘ

OpenWrt → supportsPlatform → RISC-V ⓘ

Clang → targetArchitecture → RISC-V ⓘ

LLVM → supportsArchitecture → RISC-V ⓘ

GDB → supportsArchitecture → RISC-V ⓘ

GNU C Library → supportsArchitecture → RISC-V ⓘ

FreeBSD → architectureSupport → RISC-V ⓘ

Zig → supportsArchitecture → RISC-V ⓘ

FreeRTOS → platform → RISC-V ⓘ

NetBSD → supports → RISC-V ⓘ

this entity surface form: RISC-V architecture

David A. Patterson → helpedDevelop → RISC-V ⓘ