Triple
T1717903
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | RISC-V |
E37329
|
entity |
| Predicate | hasBaseISA |
P31905
|
FINISHED |
| Object |
RV32I
RV32I is the 32-bit integer base instruction set architecture of RISC-V, defining the core operations and registers for simple, compact implementations.
|
E37329
|
NE FINISHED |
How this triple was built (5 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: RV32I | Statement: [RISC-V, hasBaseISA, RV32I]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: RV32I Context triple: [RISC-V, hasBaseISA, RV32I]
-
A.
RISC-V
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
-
B.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
C.
MMIX
MMIX is a 64-bit RISC-style hypothetical computer architecture designed by Donald Knuth as the pedagogical machine for later volumes of *The Art of Computer Programming*.
-
D.
VMX
VMX is a vector processing extension to the PowerPC architecture designed to accelerate multimedia, signal processing, and other parallelizable computations.
-
E.
Icestorm
Icestorm is the energy-efficient, low-power CPU core microarchitecture used for the efficiency cores in Apple's M1 system-on-a-chip.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg
Description generation
gpt-5.1
Instruction
Generate a one-sentence description of the target entity. You are given a context triple in the form (subject, predicate, object), where the object is the target entity. # Instructions Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. Avoid repeating the information from the triple, unless really essential. # Response Format Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: RV32I Triple: [RISC-V, hasBaseISA, RV32I]
Generated description
RV32I is the 32-bit integer base instruction set architecture of RISC-V, defining the core operations and registers for simple, compact implementations.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: RV32I Target entity description: RV32I is the 32-bit integer base instruction set architecture of RISC-V, defining the core operations and registers for simple, compact implementations.
-
A.
RISC-V
chosen
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
-
B.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
C.
MMIX
MMIX is a 64-bit RISC-style hypothetical computer architecture designed by Donald Knuth as the pedagogical machine for later volumes of *The Art of Computer Programming*.
-
D.
VMX
VMX is a vector processing extension to the PowerPC architecture designed to accelerate multimedia, signal processing, and other parallelizable computations.
-
E.
Icestorm
Icestorm is the energy-efficient, low-power CPU core microarchitecture used for the efficiency cores in Apple's M1 system-on-a-chip.
- F. None of above.
PD
Predicate disambiguation
gpt-5-mini-2025-08-07
Target predicate: hasBaseISA Context triple: [RISC-V, hasBaseISA, RV32I]
-
A.
hasSupportBase
Indicates that one entity serves as the supporting base or foundation upon which another entity rests, is mounted, or is structurally stabilized.
-
B.
isBaseFor
Indicates that one entity serves as the foundational support, starting point, or underlying basis upon which another entity is built, developed, or depends.
-
C.
isMajorBaseIn
Indicates that a location serves as a primary or central base of operations within a specified area or organization.
-
D.
hasSecondaryBase
Indicates that an entity possesses or is associated with a secondary or additional base, distinct from its primary base.
-
E.
hasBaseIndex
Indicates that one entity serves as the reference or starting index from which another entity’s position, offset, or ordering is calculated.
- F. None of above. chosen
Provenance (7 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69a8861912dc8190931af43b4b9158a7 |
completed | March 4, 2026, 7:20 p.m. |
| NER | Named-entity recognition | batch_69ab5c96db6c8190a745d6fef7bf2cdb |
completed | March 6, 2026, 11 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69ad8ae6940c81909c1ebdfb0cdef5fc |
completed | March 8, 2026, 2:42 p.m. |
| NEDg | Description generation | batch_69ad957bd63c819099a508ca5c4102cc |
completed | March 8, 2026, 3:27 p.m. |
| NED2 | Entity disambiguation (via description) | batch_69ad97b18f9c8190a9c5ed80b5ed0195 |
completed | March 8, 2026, 3:37 p.m. |
| PD | Predicate disambiguation | batch_69aa61bed2fc819086d912cd34285978 |
completed | March 6, 2026, 5:10 a.m. |
| PDg | Predicate description generation | batch_69ab5c7780bc81909fc6e173a216cb0b |
completed | March 6, 2026, 11 p.m. |
Created at: March 4, 2026, 7:30 p.m.