Triple
T1717905
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | RISC-V |
E37329
|
entity |
| Predicate | hasBaseISA |
P31905
|
FINISHED |
| Object |
RV128I
RV128I is a proposed 128-bit base integer instruction set architecture variant within the RISC-V family, designed to support very large address spaces and high-precision computation.
|
E193747
|
NE FINISHED |
Provenance (5 batches)
| Stage | Batch ID | Job type | Status |
|---|---|---|---|
| creating | batch_69a8861912dc8190931af43b4b9158a7 |
elicitation | completed |
| NER | batch_69abaffc4e5c81908ce0b9cfe833445e |
ner | completed |
| NED1 | batch_69ad8ae6940c81909c1ebdfb0cdef5fc |
ned_source_triple | completed |
| NED2 | batch_69ad97b18f9c8190a9c5ed80b5ed0195 |
ned_description | completed |
| NEDg | batch_69ad957bd63c819099a508ca5c4102cc |
nedg | completed |
Created at: March 4, 2026, 7:30 p.m.