RV128I
E193747
RISC-V base integer instruction set architecture
computer architecture proposal
instruction set architecture
RV128I is a proposed 128-bit base integer instruction set architecture variant within the RISC-V family, designed to support very large address spaces and high-precision computation.
All labels observed (1)
| Label | Occurrences |
|---|---|
| RV128I canonical | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T1717905 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: RV128I Context triple: [RISC-V, hasBaseISA, RV128I]
-
A.
RVR
RVR is the standard abbreviation for the Reina-Valera, a widely used Spanish translation of the Bible.
-
B.
PV-12
PV-12 is the original development designation for the Rolls-Royce Merlin, the famous British liquid-cooled V12 aircraft engine used extensively in World War II fighters and bombers.
-
C.
OV-102
OV-102 is the NASA Space Shuttle orbiter better known as Columbia, the first operational shuttle to fly into space.
-
D.
RV Kairei
RV Kairei is a Japanese deep-sea research vessel operated by JAMSTEC, known for conducting advanced oceanographic and seafloor exploration in some of the world’s deepest waters.
-
E.
Ralph 124C 41+
Ralph 124C 41+ is a pioneering early science fiction novel by Hugo Gernsback that famously envisioned numerous future technologies and helped shape the genre’s development.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: RV128I Target entity description: RV128I is a proposed 128-bit base integer instruction set architecture variant within the RISC-V family, designed to support very large address spaces and high-precision computation.
-
A.
RVR
RVR is the standard abbreviation for the Reina-Valera, a widely used Spanish translation of the Bible.
-
B.
PV-12
PV-12 is the original development designation for the Rolls-Royce Merlin, the famous British liquid-cooled V12 aircraft engine used extensively in World War II fighters and bombers.
-
C.
OV-102
OV-102 is the NASA Space Shuttle orbiter better known as Columbia, the first operational shuttle to fly into space.
-
D.
RV Kairei
RV Kairei is a Japanese deep-sea research vessel operated by JAMSTEC, known for conducting advanced oceanographic and seafloor exploration in some of the world’s deepest waters.
-
E.
Ralph 124C 41+
Ralph 124C 41+ is a pioneering early science fiction novel by Hugo Gernsback that famously envisioned numerous future technologies and helped shape the genre’s development.
- F. None of above. chosen
Statements (31)
| Predicate | Object |
|---|---|
| instanceOf |
RISC-V base integer instruction set architecture
ⓘ
computer architecture proposal ⓘ instruction set architecture ⓘ |
| addressSpaceCapability | larger than 64-bit address space ⓘ |
| architectureFamily | RISC-V ⓘ |
| backwardCompatibilityGoal | conceptual compatibility with existing RISC-V software model where feasible ⓘ |
| baseISAType | integer ⓘ |
| bitWidth | 128-bit ⓘ |
| compatibleWith |
RISC-V
ⓘ
surface form:
RISC-V modular extension scheme
|
| designedFor | future-proofing address space limitations beyond 64-bit ⓘ |
| designGoal |
support high-precision computation
ⓘ
support very large address spaces ⓘ |
| designParadigm | reduced instruction set computing (RISC) ⓘ |
| documentationStatus | discussed in RISC-V community and roadmap documents ⓘ |
| endiannessModel | expected to follow RISC-V endianness conventions (typically little-endian) ⓘ |
| extensionPotential | can be combined with 128-bit-capable vector extensions when defined ⓘ |
| generalPurposeRegisterCount | intended to match other RISC-V base ISAs (32 GPRs) when fully specified ⓘ |
| namingConvention | RISC-V base ISA naming (RV + XLEN + I) ⓘ |
| numericTypeFocus | integer operations with 128-bit word size ⓘ |
| primaryMotivation | overcome limitations of 64-bit address and integer ranges ⓘ |
| registerWidth | 128-bit integer registers ⓘ |
| relatedTo |
RISC-V
ⓘ
surface form:
RV32I
RISC-V ⓘ
surface form:
RV64I
|
| specificationBody |
RISC-V International
ⓘ
surface form:
RISC-V International (for future standardization)
|
| standardizationStatus | not yet ratified in the RISC-V ISA standard ⓘ |
| status | proposed ⓘ |
| supportsExtensionModel | RISC-V standard extensions (e.g., M, A, F, D, V) when defined for 128-bit ⓘ |
| targetUseCase |
high-end servers and supercomputers
ⓘ
high-precision numerical workloads ⓘ systems requiring extremely large virtual memory ⓘ |
| xlen | 128 ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: RV128I Description of subject: RV128I is a proposed 128-bit base integer instruction set architecture variant within the RISC-V family, designed to support very large address spaces and high-precision computation.
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.