instruction set architecture specification
C2627
concept
An instruction set architecture specification defines the set of machine instructions, data types, registers, addressing modes, and execution behavior that software uses to interact with a processor implementation.
Observed surface forms (3)
- instruction set architecture ×8
- 64-bit instruction set architecture ×1
- vector instruction set ×1
Instances (10)
- ARM via concept surface "instruction set architecture"
- RISC-V via concept surface "instruction set architecture"
- MIPS via concept surface "instruction set architecture"
- WebAssembly specification
- VMX via concept surface "vector instruction set"
- Power ISA via concept surface "instruction set architecture"
- Power Architecture via concept surface "instruction set architecture"
-
SPARC microprocessor architecture
via concept surface "instruction set architecture"
surface form: SPARC
- Acorn RISC Machine via concept surface "instruction set architecture"
- AMD64 architecture via concept surface "instruction set architecture"