instruction set architecture specification
C2627
concept
An instruction set architecture specification defines the set of machine instructions, data types, registers, addressing modes, and execution behavior that software uses to interact with a processor implementation.
All labels observed (12)
| Label | Occurrences |
|---|---|
| instruction set architecture | 35 |
| assembly language | 3 |
| vector instruction set | 3 |
| 64-bit instruction set architecture | 2 |
| CISC instruction set architecture | 1 |
| MIPS ABI | 1 |
| component of Power Architecture specification | 1 |
| computer instruction set architecture | 1 |
| instruction set architecture paradigm | 1 |
| instruction set architecture specification canonical | 1 |
| instruction set reference | 1 |
| processor documentation | 1 |
Instances (48)
| Instance | Via concept surface |
|---|---|
| ARM | instruction set architecture |
| IA-32 | instruction set architecture |
| x86 | instruction set architecture |
| Itanium | 64-bit instruction set architecture |
| RV128I | instruction set architecture |
| Microprocessor without Interlocked Pipeline Stages | instruction set architecture |
| o32 ABI | MIPS ABI |
| z/Architecture | instruction set architecture |
| NEON SIMD | vector instruction set |
| Assembler | assembly language |
| POWER instruction set architecture | instruction set architecture |
| Book II | component of Power Architecture specification |
| ARMv8-A | instruction set architecture |
| HP PA-RISC | instruction set architecture |
| ARMv9-A | instruction set architecture |
| Thumb instruction set | instruction set architecture |
| ARMv6 architecture family | instruction set architecture |
|
ARMv7-A architecture
surface form:
ARMv7-A
|
instruction set architecture |
| Java bytecode | instruction set architecture |
|
ARMv5 architecture
surface form:
ARMv5
|
instruction set architecture |
| RISC-V | instruction set architecture |
| MIPS | instruction set architecture |
| WebAssembly specification | — |
| VMX | vector instruction set |
| Power ISA | instruction set architecture |
| Power Architecture | instruction set architecture |
| Intel Architecture Software Developer’s Manual | processor documentation |
| CISC | instruction set architecture |
| AVX-512 | vector instruction set |
| MIXAL | assembly language |
|
SPARC microprocessor architecture
surface form:
SPARC
|
instruction set architecture |
| Virtual Address eXtension | instruction set architecture |
| Acorn RISC Machine | instruction set architecture |
| MIPS II | instruction set architecture |
| ESA/390 | instruction set architecture |
| HPPA | instruction set architecture |
| MIPS III | instruction set architecture |
| MIPS IV | instruction set architecture |
| MIPS V | instruction set architecture |
| IBM ESA/390 ISA | instruction set architecture |
| ARMv8.1-M | instruction set architecture |
| ARMv8.2-M | instruction set architecture |
| IBM POWER instruction set | instruction set architecture |
| MACRO-11 | assembly language |
| PowerPC ISA v2.0 | instruction set architecture |
| IBM ESA/370 instruction set | computer instruction set architecture |
| AMD64 architecture | instruction set architecture |
| VLIW | instruction set architecture paradigm |