Triple

T1717915
Position Surface form Disambiguated ID Type / Status
Subject RISC-V E37329 entity
Predicate hasExtension P455 FINISHED
Object B (bit-manipulation extension)
B (bit-manipulation extension) is a RISC-V ISA extension that adds specialized instructions to efficiently perform common bit-level operations such as shifts, rotates, and bitfield manipulation.
 E193750 NE FINISHED

How this triple was built (4 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: B (bit-manipulation extension) | Statement: [RISC-V, hasExtension, B (bit-manipulation extension)]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07 
Target entity: B (bit-manipulation extension)
Context triple: [RISC-V, hasExtension, B (bit-manipulation extension)]
  • A. B programming language
    The B programming language is an early, minimalist high-level language developed at Bell Labs that directly influenced the design of the C programming language.
  • B. BitC
    BitC is a systems programming language designed for safety, low-level control, and formal verification, drawing on ideas from Modula-3 and capability-based security.
  • C. SSE2
    SSE2 is an x86 processor instruction set extension introduced by Intel that adds advanced SIMD (Single Instruction, Multiple Data) capabilities for faster floating-point and integer computations.
  • D. MMIX
    MMIX is a 64-bit RISC-style hypothetical computer architecture designed by Donald Knuth as the pedagogical machine for later volumes of *The Art of Computer Programming*.
  • E. MIPS
    MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
  • F. None of above. chosen
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg Description generation gpt-5.1
Instruction
Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: B (bit-manipulation extension)
Triple: [RISC-V, hasExtension, B (bit-manipulation extension)]
Generated description
B (bit-manipulation extension) is a RISC-V ISA extension that adds specialized instructions to efficiently perform common bit-level operations such as shifts, rotates, and bitfield manipulation.
NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07 
Target entity: B (bit-manipulation extension)
Target entity description: B (bit-manipulation extension) is a RISC-V ISA extension that adds specialized instructions to efficiently perform common bit-level operations such as shifts, rotates, and bitfield manipulation.
  • A. B programming language
    The B programming language is an early, minimalist high-level language developed at Bell Labs that directly influenced the design of the C programming language.
  • B. BitC
    BitC is a systems programming language designed for safety, low-level control, and formal verification, drawing on ideas from Modula-3 and capability-based security.
  • C. SSE2
    SSE2 is an x86 processor instruction set extension introduced by Intel that adds advanced SIMD (Single Instruction, Multiple Data) capabilities for faster floating-point and integer computations.
  • D. MMIX
    MMIX is a 64-bit RISC-style hypothetical computer architecture designed by Donald Knuth as the pedagogical machine for later volumes of *The Art of Computer Programming*.
  • E. MIPS
    MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
  • F. None of above. chosen

Provenance (5 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69a8861912dc8190931af43b4b9158a7 completed March 4, 2026, 7:20 p.m.
NER Named-entity recognition batch_69aa6337d8408190bdba8b50652d50ae completed March 6, 2026, 5:16 a.m.
NED1 Entity disambiguation (via context triple) batch_69ad8ae6940c81909c1ebdfb0cdef5fc completed March 8, 2026, 2:42 p.m.
NEDg Description generation batch_69ad957bd63c819099a508ca5c4102cc completed March 8, 2026, 3:27 p.m.
NED2 Entity disambiguation (via description) batch_69ad97b18f9c8190a9c5ed80b5ed0195 completed March 8, 2026, 3:37 p.m.
Created at: March 4, 2026, 7:30 p.m.