Triple

T1717914
Position Surface form Disambiguated ID Type / Status
Subject RISC-V E37329 entity
Predicate hasExtension P455 FINISHED
Object V (vector extension)
V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
 E193749 NE FINISHED

How this triple was built (4 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: V (vector extension) | Statement: [RISC-V, hasExtension, V (vector extension)]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07 
Target entity: V (vector extension)
Context triple: [RISC-V, hasExtension, V (vector extension)]
  • A. Intel AVX2
    Intel AVX2 is an x86 instruction set extension from Intel that enhances performance for integer-heavy and vectorized workloads through wider SIMD operations and new vector instructions.
  • B. Intel AVX
    Intel AVX is an x86 processor instruction set extension from Intel that accelerates floating-point and vector-intensive workloads, commonly used in high-performance computing, multimedia, and scientific applications.
  • C. SSE2
    SSE2 is an x86 processor instruction set extension introduced by Intel that adds advanced SIMD (Single Instruction, Multiple Data) capabilities for faster floating-point and integer computations.
  • D. VMX
    VMX is a vector processing extension to the PowerPC architecture designed to accelerate multimedia, signal processing, and other parallelizable computations.
  • E. AltiVec
    AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
  • F. None of above. chosen
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg Description generation gpt-5.1
Instruction
Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: V (vector extension)
Triple: [RISC-V, hasExtension, V (vector extension)]
Generated description
V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07 
Target entity: V (vector extension)
Target entity description: V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
  • A. Intel AVX2
    Intel AVX2 is an x86 instruction set extension from Intel that enhances performance for integer-heavy and vectorized workloads through wider SIMD operations and new vector instructions.
  • B. Intel AVX
    Intel AVX is an x86 processor instruction set extension from Intel that accelerates floating-point and vector-intensive workloads, commonly used in high-performance computing, multimedia, and scientific applications.
  • C. SSE2
    SSE2 is an x86 processor instruction set extension introduced by Intel that adds advanced SIMD (Single Instruction, Multiple Data) capabilities for faster floating-point and integer computations.
  • D. VMX
    VMX is a vector processing extension to the PowerPC architecture designed to accelerate multimedia, signal processing, and other parallelizable computations.
  • E. AltiVec
    AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
  • F. None of above. chosen

Provenance (5 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69a8861912dc8190931af43b4b9158a7 completed March 4, 2026, 7:20 p.m.
NER Named-entity recognition batch_69aa6337d8408190bdba8b50652d50ae completed March 6, 2026, 5:16 a.m.
NED1 Entity disambiguation (via context triple) batch_69ad8ae6940c81909c1ebdfb0cdef5fc completed March 8, 2026, 2:42 p.m.
NEDg Description generation batch_69ad957bd63c819099a508ca5c4102cc completed March 8, 2026, 3:27 p.m.
NED2 Entity disambiguation (via description) batch_69ad97b18f9c8190a9c5ed80b5ed0195 completed March 8, 2026, 3:37 p.m.
Created at: March 4, 2026, 7:30 p.m.