V (vector extension)
E193749
V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
All labels observed (5)
| Label | Occurrences |
|---|---|
| RISC-V ISA extensions | 1 |
| RISC-V V (vector) extension | 1 |
| RISC-V V extension | 1 |
| RISC-V Vector Extension | 1 |
| V (vector extension) canonical | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T1717914 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: V (vector extension) Context triple: [RISC-V, hasExtension, V (vector extension)]
-
A.
Intel AVX2
Intel AVX2 is an x86 instruction set extension from Intel that enhances performance for integer-heavy and vectorized workloads through wider SIMD operations and new vector instructions.
-
B.
Intel AVX
Intel AVX is an x86 processor instruction set extension from Intel that accelerates floating-point and vector-intensive workloads, commonly used in high-performance computing, multimedia, and scientific applications.
-
C.
SSE2
SSE2 is an x86 processor instruction set extension introduced by Intel that adds advanced SIMD (Single Instruction, Multiple Data) capabilities for faster floating-point and integer computations.
-
D.
VMX
VMX is a vector processing extension to the PowerPC architecture designed to accelerate multimedia, signal processing, and other parallelizable computations.
-
E.
AltiVec
AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: V (vector extension) Target entity description: V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
-
A.
Intel AVX2
Intel AVX2 is an x86 instruction set extension from Intel that enhances performance for integer-heavy and vectorized workloads through wider SIMD operations and new vector instructions.
-
B.
Intel AVX
Intel AVX is an x86 processor instruction set extension from Intel that accelerates floating-point and vector-intensive workloads, commonly used in high-performance computing, multimedia, and scientific applications.
-
C.
SSE2
SSE2 is an x86 processor instruction set extension introduced by Intel that adds advanced SIMD (Single Instruction, Multiple Data) capabilities for faster floating-point and integer computations.
-
D.
VMX
VMX is a vector processing extension to the PowerPC architecture designed to accelerate multimedia, signal processing, and other parallelizable computations.
-
E.
AltiVec
AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
- F. None of above. chosen
Statements (49)
| Predicate | Object |
|---|---|
| instanceOf |
RISC-V extension
ⓘ
vector instruction set architecture ⓘ |
| alsoKnownAs |
V (vector extension)
ⓘ
surface form:
RISC-V V extension
V (vector extension) ⓘ
surface form:
RISC-V Vector Extension
|
| architectureStyle | scalable vector architecture ⓘ |
| compatibleWith |
RISC-V
ⓘ
surface form:
RISC-V base integer ISA
RISC-V ⓘ
surface form:
RISC-V floating-point extensions
|
| definedBy | RISC-V International ⓘ |
| designGoal |
energy-efficient parallel computation
ⓘ
performance portability ⓘ scalability across microarchitectures ⓘ support for a wide range of vector lengths ⓘ |
| enables |
efficient utilization of vector hardware resources
ⓘ
hardware-agnostic vectorized code ⓘ parallel computation on variable-length data vectors ⓘ |
| hasProperty |
decoupling of software vector length from hardware width
ⓘ
implementation-defined maximum vector length ⓘ support for both 32-bit and 64-bit base ISAs ⓘ support for different element sizes ⓘ support for mixed-precision operations ⓘ |
| keyConcept |
mask registers
ⓘ
vector configuration instructions ⓘ vector register grouping ⓘ vector-length-agnostic programming model ⓘ |
| partOf |
RISC-V
ⓘ
surface form:
RISC-V ISA
|
| supports |
SIMD-like computation
ⓘ
data-level parallelism ⓘ fixed-point vector operations ⓘ floating-point vector operations ⓘ integer vector operations ⓘ predicated execution ⓘ segmented vector operations ⓘ tail-agnostic execution ⓘ tail-undisturbed execution ⓘ variable-length vectors ⓘ vector arithmetic operations ⓘ vector load and store operations ⓘ vector mask operations ⓘ vector permutation operations ⓘ vector processing ⓘ vector reduction operations ⓘ vector registers ⓘ vectorized loops ⓘ |
| usedFor |
data analytics
ⓘ
high-performance computing ⓘ image processing ⓘ machine learning workloads ⓘ scientific computing ⓘ signal processing ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: V (vector extension) Description of subject: V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
Referenced by (5)
Full triples — surface form annotated when it differs from this entity's canonical label.
this entity surface form:
RISC-V ISA extensions
this entity surface form:
RISC-V V extension
this entity surface form:
RISC-V Vector Extension
this entity surface form:
RISC-V V (vector) extension