Triple

T1717941
Position Surface form Disambiguated ID Type / Status
Subject RISC-V E37329 entity
Predicate hasSimulator P31906 FINISHED
Object Spike RISC-V ISA simulator
Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
E193754 NE FINISHED

How this triple was built (5 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Spike RISC-V ISA simulator | Statement: [RISC-V, hasSimulator, Spike RISC-V ISA simulator]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07
Target entity: Spike RISC-V ISA simulator
Context triple: [RISC-V, hasSimulator, Spike RISC-V ISA simulator]
  • A. RISC-V
    RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
  • B. SPIM
    SPIM was the former ICAO airport code for Jorge Chávez International Airport in Lima, Peru, before it was changed to SPJC.
  • C. MIPS
    MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
  • D. SPARC microprocessor architecture
    The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
  • E. Acorn RISC Machine
    Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
  • F. None of above. chosen
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg Description generation gpt-5.1
Instruction
Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: Spike RISC-V ISA simulator
Triple: [RISC-V, hasSimulator, Spike RISC-V ISA simulator]
Generated description
Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07
Target entity: Spike RISC-V ISA simulator
Target entity description: Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
  • A. RISC-V
    RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
  • B. SPIM
    SPIM was the former ICAO airport code for Jorge Chávez International Airport in Lima, Peru, before it was changed to SPJC.
  • C. MIPS
    MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
  • D. SPARC microprocessor architecture
    The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
  • E. Acorn RISC Machine
    Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
  • F. None of above. chosen
PD Predicate disambiguation gpt-5-mini-2025-08-07
Target predicate: hasSimulator
Context triple: [RISC-V, hasSimulator, Spike RISC-V ISA simulator]
  • A. hasHardwareSeries
    Indicates that one hardware item belongs to, or is categorized under, a particular hardware series or product line.
  • B. hasPlatformType
    Indicates that an entity is associated with or characterized by a specific type or category of platform.
  • C. hasFormFactor
    Indicates that one entity possesses or is characterized by a particular physical or structural form factor defined by another entity.
  • D. deviceIndicates
    Indicates that a device provides a signal, status, or output that conveys information about a condition, event, or state.
  • E. usesDevice
    Indicates that one entity operates, employs, or relies on a particular device to perform an action or achieve a purpose.
  • F. None of above. chosen

Provenance (7 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69a8861912dc8190931af43b4b9158a7 completed March 4, 2026, 7:20 p.m.
NER Named-entity recognition batch_69ab5c96db6c8190a745d6fef7bf2cdb completed March 6, 2026, 11 p.m.
NED1 Entity disambiguation (via context triple) batch_69ad8ae6940c81909c1ebdfb0cdef5fc completed March 8, 2026, 2:42 p.m.
NEDg Description generation batch_69ad957bd63c819099a508ca5c4102cc completed March 8, 2026, 3:27 p.m.
NED2 Entity disambiguation (via description) batch_69ad97b18f9c8190a9c5ed80b5ed0195 completed March 8, 2026, 3:37 p.m.
PD Predicate disambiguation batch_69aa61bed2fc819086d912cd34285978 completed March 6, 2026, 5:10 a.m.
PDg Predicate description generation batch_69ab5c7780bc81909fc6e173a216cb0b completed March 6, 2026, 11 p.m.
Created at: March 4, 2026, 7:30 p.m.