Triple

T1717942
Position Surface form Disambiguated ID Type / Status
Subject RISC-V E37329 entity
Predicate hasSimulator P31906 FINISHED
Object QEMU RISC-V target
QEMU RISC-V target is an emulation backend in the QEMU virtualization platform that allows users to run and test RISC-V software on non-RISC-V host systems.
 E193755 NE FINISHED

How this triple was built (4 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: QEMU RISC-V target | Statement: [RISC-V, hasSimulator, QEMU RISC-V target]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07 
Target entity: QEMU RISC-V target
Context triple: [RISC-V, hasSimulator, QEMU RISC-V target]
  • A. RISC-V
    RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
  • B. MIPS
    MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
  • C. Bytecode Alliance
    Bytecode Alliance is a nonprofit industry consortium focused on advancing secure, modular, and portable software through technologies built around WebAssembly.
  • D. Acorn RISC Machine
    Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
  • E. Calliope mini
    Calliope mini is a small educational microcontroller board designed to teach children and beginners programming and electronics through interactive projects.
  • F. None of above. chosen
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg Description generation gpt-5.1
Instruction
Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: QEMU RISC-V target
Triple: [RISC-V, hasSimulator, QEMU RISC-V target]
Generated description
QEMU RISC-V target is an emulation backend in the QEMU virtualization platform that allows users to run and test RISC-V software on non-RISC-V host systems.
NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07 
Target entity: QEMU RISC-V target
Target entity description: QEMU RISC-V target is an emulation backend in the QEMU virtualization platform that allows users to run and test RISC-V software on non-RISC-V host systems.
  • A. RISC-V
    RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
  • B. MIPS
    MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
  • C. Bytecode Alliance
    Bytecode Alliance is a nonprofit industry consortium focused on advancing secure, modular, and portable software through technologies built around WebAssembly.
  • D. Acorn RISC Machine
    Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
  • E. Calliope mini
    Calliope mini is a small educational microcontroller board designed to teach children and beginners programming and electronics through interactive projects.
  • F. None of above. chosen

Provenance (5 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69a8861912dc8190931af43b4b9158a7 completed March 4, 2026, 7:20 p.m.
NER Named-entity recognition batch_69abaffc4e5c81908ce0b9cfe833445e completed March 7, 2026, 4:56 a.m.
NED1 Entity disambiguation (via context triple) batch_69ad8ae6940c81909c1ebdfb0cdef5fc completed March 8, 2026, 2:42 p.m.
NEDg Description generation batch_69ad957bd63c819099a508ca5c4102cc completed March 8, 2026, 3:27 p.m.
NED2 Entity disambiguation (via description) batch_69ad97b18f9c8190a9c5ed80b5ed0195 completed March 8, 2026, 3:37 p.m.
Created at: March 4, 2026, 7:30 p.m.