Triple

Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).

Phrase: RV64I | Statement: [RISC-V, hasBaseISA, RV64I]

Target entity: RV64I
Context triple: [RISC-V, hasBaseISA, RV64I]

• A. RISC-V
  RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
• B. MIPS
  MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
• C. V (vector extension)
  V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
• D. Spike RISC-V ISA simulator
  Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
• E. Itanium
  Itanium is a 64-bit server processor architecture developed by Intel (with early collaboration from HP) that was designed for high-end enterprise and technical computing but ultimately saw limited adoption and was discontinued.
• F. None of above. chosen
• G. Unsure - the case is ambiguous/there is not enough information to decide.

Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"

Entity: RV64I
Triple: [RISC-V, hasBaseISA, RV64I]

RV64I is the 64-bit base integer instruction set architecture of the open RISC-V processor family, defining its core operations and programming model.

Target entity: RV64I
Target entity description: RV64I is the 64-bit base integer instruction set architecture of the open RISC-V processor family, defining its core operations and programming model.

• A. RISC-V chosen
  RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
• B. MIPS
  MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
• C. V (vector extension)
  V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
• D. Spike RISC-V ISA simulator
  Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
• E. Itanium
  Itanium is a 64-bit server processor architecture developed by Intel (with early collaboration from HP) that was designed for high-end enterprise and technical computing but ultimately saw limited adoption and was discontinued.
• F. None of above.