Triple
T1718000
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | MIPS |
E37330
|
entity |
| Predicate | influenced |
P9
|
FINISHED |
| Object | RISC-V |
E37329
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: RISC-V | Statement: [MIPS, influenced, RISC-V]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: RISC-V Context triple: [MIPS, influenced, RISC-V]
-
A.
RISC-V
chosen
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
-
B.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
C.
Bytecode Alliance
Bytecode Alliance is a nonprofit industry consortium focused on advancing secure, modular, and portable software through technologies built around WebAssembly.
-
D.
SPARC microprocessor architecture
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
-
E.
Calliope mini
Calliope mini is a small educational microcontroller board designed to teach children and beginners programming and electronics through interactive projects.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69a8861912dc8190931af43b4b9158a7 |
completed | March 4, 2026, 7:20 p.m. |
| NER | Named-entity recognition | batch_69aa6337d8408190bdba8b50652d50ae |
completed | March 6, 2026, 5:16 a.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69ad8ae6940c81909c1ebdfb0cdef5fc |
completed | March 8, 2026, 2:42 p.m. |
Created at: March 4, 2026, 7:30 p.m.