Verilog

E237419

HDL IEEE standard hardware description language programming language

Verilog is a hardware description language (HDL) used to model, design, and verify digital circuits and systems such as those implemented in CPLDs and FPGAs.

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All labels observed (4)

Label	Occurrences
Verilog canonical	10
Verilog-1995	1
Verilog-2001	1
Verilog-2005	1

How this entity was disambiguated

This entity first appeared as the object of triple T2130597 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.

NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07

Target entity: Verilog
Context triple: [CPLD, configuredBy, Verilog]

A. FPGA
An FPGA (Field-Programmable Gate Array) is a reconfigurable integrated circuit that can be programmed after manufacturing to implement custom digital logic functions and hardware designs.
B. Quartus design software
Quartus design software is Altera’s integrated development environment used for designing, simulating, and implementing FPGA and CPLD digital logic circuits.
C. MAX+PLUS II
MAX+PLUS II is a legacy computer-aided design software suite from Altera used for developing, simulating, and programming programmable logic devices such as FPGAs and CPLDs.
D. SVA
SVA is the ICAO airline designator used to identify Saudia, the flag carrier airline of Saudi Arabia, in international aviation operations.
E. CPLDs
CPLDs (Complex Programmable Logic Devices) are reconfigurable digital integrated circuits used to implement custom logic functions in hardware, often for control, glue logic, and interface applications.
F. None of above. chosen
G. Unsure - the case is ambiguous/there is not enough information to decide.

NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07

Target entity: Verilog
Target entity description: Verilog is a hardware description language (HDL) used to model, design, and verify digital circuits and systems such as those implemented in CPLDs and FPGAs.

A. FPGA
An FPGA (Field-Programmable Gate Array) is a reconfigurable integrated circuit that can be programmed after manufacturing to implement custom digital logic functions and hardware designs.
B. Quartus design software
Quartus design software is Altera’s integrated development environment used for designing, simulating, and implementing FPGA and CPLD digital logic circuits.
C. MAX+PLUS II
MAX+PLUS II is a legacy computer-aided design software suite from Altera used for developing, simulating, and programming programmable logic devices such as FPGAs and CPLDs.
D. SVA
SVA is the ICAO airline designator used to identify Saudia, the flag carrier airline of Saudi Arabia, in international aviation operations.
E. CPLDs
CPLDs (Complex Programmable Logic Devices) are reconfigurable digital integrated circuits used to implement custom logic functions in hardware, often for control, glue logic, and interface applications.
F. None of above. chosen

Statements (70)

Predicate	Object
instanceOf	HDL ⓘ IEEE standard ⓘ hardware description language ⓘ programming language ⓘ
category	textual HDL ⓘ
commonlyUsedWith	ASIC design flow ⓘ FPGA toolchain ⓘ HDL simulator ⓘ logic synthesizer ⓘ
competesWith	VHDL ⓘ
designAbstractionLevel	behavioral ⓘ gate level ⓘ register-transfer level ⓘ
executionModel	simulation-based ⓘ
field	computer engineering ⓘ digital design ⓘ electronic design automation ⓘ
firstStandardizedIn	1995 ⓘ
hasConcept	always block ⓘ function ⓘ generate block ⓘ initial block ⓘ module ⓘ reg ⓘ system function ⓘ system task ⓘ task ⓘ timescale directive ⓘ wire ⓘ
hasFileExtension	.v ⓘ .vh ⓘ
hasVersion	Verilog self-linksurface differs ⓘ surface form: Verilog-1995 Verilog self-linksurface differs ⓘ surface form: Verilog-2001 Verilog self-linksurface differs ⓘ surface form: Verilog-2005
influenced	Bluespec SystemVerilog ⓘ Chisel ⓘ SystemVerilog ⓘ Verilog-AMS ⓘ
influencedBy	C ⓘ surface form: C programming language hardware description languages ⓘ
standardizedBy	Institute of Electrical and Electronics Engineers ⓘ surface form: IEEE
standardNumber	IEEE 1364 ⓘ
status	largely subsumed by SystemVerilog for new designs ⓘ
supports	bit-level operations ⓘ blocking assignments ⓘ concurrent execution ⓘ continuous assignments ⓘ event-driven simulation ⓘ module hierarchy ⓘ non-blocking assignments ⓘ parameterization ⓘ procedural blocks ⓘ synthesis constructs ⓘ testbench constructs ⓘ timing control ⓘ
typicalTarget	ASIC ⓘ CPLDs ⓘ surface form: CPLD FPGA ⓘ
usedFor	ASIC design ⓘ CPLD design ⓘ FPGA design ⓘ behavioral modeling ⓘ designing digital circuits ⓘ gate-level modeling ⓘ modeling digital circuits ⓘ register-transfer level design ⓘ simulation of digital systems ⓘ synthesis of digital hardware ⓘ testbench creation ⓘ verifying digital circuits ⓘ

How these facts were elicited

Referenced by (13)

Full triples — surface form annotated when it differs from this entity's canonical label.

CPLDs → configuredBy → Verilog ⓘ

subject surface form: CPLD

VLSI technology → usesLanguage → Verilog ⓘ

Mentor Graphics → languageSupport → Verilog ⓘ

FPGA → uses → Verilog ⓘ

Quartus design software → supportsLanguage → Verilog ⓘ

MAX+PLUS II → supportsLanguage → Verilog ⓘ

Cyclone → supports → Verilog ⓘ

VHDL → competesWith → Verilog ⓘ

Verilog → hasVersion → Verilog self-linksurface differs ⓘ

this entity surface form: Verilog-1995

Verilog → hasVersion → Verilog self-linksurface differs ⓘ

this entity surface form: Verilog-2001

Verilog → hasVersion → Verilog self-linksurface differs ⓘ

this entity surface form: Verilog-2005

Clang-Format → supportsLanguage → Verilog ⓘ

SystemVerilog → basedOn → Verilog ⓘ

All labels observed (4)

How this entity was disambiguated Show

Statements (70)

How these facts were elicited Show

Referenced by (13)

How this entity was disambiguated

How these facts were elicited