Chisel

E820859

embedded domain-specific language hardware description language

Chisel is a modern hardware description language embedded in Scala that enables advanced, parameterizable digital circuit design and generation.

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Statements (46)

Predicate	Object
instanceOf	embedded domain-specific language ⓘ hardware description language ⓘ
advantage	higher-level hardware abstraction ⓘ parameterized design reuse ⓘ reusable hardware components ⓘ
associatedWith	Berkeley Architecture Research Group NERFINISHED ⓘ RISC-V ecosystem NERFINISHED ⓘ
comparedTo	VHDL NERFINISHED ⓘ Verilog NERFINISHED ⓘ
designedFor	ASIC design ⓘ FPGA design ⓘ
developedAt	University of California, Berkeley NERFINISHED ⓘ
ecosystemIncludes	Chisel standard library NERFINISHED ⓘ FIRRTL compiler NERFINISHED ⓘ testing frameworks ⓘ
embeddedIn	Scala NERFINISHED ⓘ
hasTool	Chisel standard library ⓘ Chisel test framework ⓘ
hasVersion	Chisel3 NERFINISHED ⓘ
implementationLanguage	Scala NERFINISHED ⓘ
influencedBy	Bluespec SystemVerilog NERFINISHED ⓘ Scala NERFINISHED ⓘ
license	BSD-style open-source license ⓘ
outputFormat	FIRRTL NERFINISHED ⓘ Verilog NERFINISHED ⓘ
predecessor	Chisel2 NERFINISHED ⓘ
programmingParadigm	hardware construction language ⓘ
runsOn	Java Virtual Machine NERFINISHED ⓘ
supports	digital circuit generation ⓘ functional programming constructs ⓘ generator-based hardware design ⓘ hardware generators ⓘ hardware verification through Scala-based tests ⓘ mixed abstraction levels in design ⓘ object-oriented hardware design patterns ⓘ parameterizable circuit design ⓘ parameterized modules ⓘ testbench construction ⓘ type-safe hardware construction ⓘ
targetDomain	digital hardware design ⓘ
usedBy	academic research projects ⓘ industry hardware design teams ⓘ
usedFor	RISC-V processor design ⓘ SoC design ⓘ accelerator design ⓘ
usesIntermediateRepresentation	FIRRTL NERFINISHED ⓘ

Referenced by (1)

Full triples — surface form annotated when it differs from this entity's canonical label.

Verilog → influenced → Chisel ⓘ