Triple
T9782903
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Verilog |
E237419
|
entity |
| Predicate | influenced |
P9
|
FINISHED |
| Object |
Bluespec SystemVerilog
Bluespec SystemVerilog is a high-level hardware description language that extends Verilog with rule-based, functional programming concepts to enable more abstract and formally verifiable hardware design.
|
E820860
|
NE FINISHED |
Provenance (5 batches)
| Stage | Batch ID | Job type | Status |
|---|---|---|---|
| creating | batch_69ca84da927881909bda80caecad6010 |
elicitation | completed |
| NER | batch_69cda1b5714481908bf74b8bf3e4e6e8 |
ner | completed |
| NED1 | batch_69d1c41b31b08190937f374c2d51aa1b |
ned_source_triple | completed |
| NED2 | batch_69d1c4fe71308190ac08e30c98611ed6 |
ned_description | completed |
| NEDg | batch_69d1c4a087208190b81ae9d40de08ab9 |
nedg | completed |
Created at: March 30, 2026, 8:27 p.m.