Triple

Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).

Phrase: Verilog | Statement: [CPLD, configuredBy, Verilog]

Target entity: Verilog
Context triple: [CPLD, configuredBy, Verilog]

• A. FPGA
  An FPGA (Field-Programmable Gate Array) is a reconfigurable integrated circuit that can be programmed after manufacturing to implement custom digital logic functions and hardware designs.
• B. Quartus design software
  Quartus design software is Altera’s integrated development environment used for designing, simulating, and implementing FPGA and CPLD digital logic circuits.
• C. MAX+PLUS II
  MAX+PLUS II is a legacy computer-aided design software suite from Altera used for developing, simulating, and programming programmable logic devices such as FPGAs and CPLDs.
• D. SVA
  SVA is the ICAO airline designator used to identify Saudia, the flag carrier airline of Saudi Arabia, in international aviation operations.
• E. CPLDs
  CPLDs (Complex Programmable Logic Devices) are reconfigurable digital integrated circuits used to implement custom logic functions in hardware, often for control, glue logic, and interface applications.
• F. None of above. chosen
• G. Unsure - the case is ambiguous/there is not enough information to decide.

Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"

Entity: Verilog
Triple: [CPLD, configuredBy, Verilog]

Verilog is a hardware description language (HDL) used to model, design, and verify digital circuits and systems such as those implemented in CPLDs and FPGAs.

Target entity: Verilog
Target entity description: Verilog is a hardware description language (HDL) used to model, design, and verify digital circuits and systems such as those implemented in CPLDs and FPGAs.

• A. FPGA
  An FPGA (Field-Programmable Gate Array) is a reconfigurable integrated circuit that can be programmed after manufacturing to implement custom digital logic functions and hardware designs.
• B. Quartus design software
  Quartus design software is Altera’s integrated development environment used for designing, simulating, and implementing FPGA and CPLD digital logic circuits.
• C. MAX+PLUS II
  MAX+PLUS II is a legacy computer-aided design software suite from Altera used for developing, simulating, and programming programmable logic devices such as FPGAs and CPLDs.
• D. SVA
  SVA is the ICAO airline designator used to identify Saudia, the flag carrier airline of Saudi Arabia, in international aviation operations.
• E. CPLDs
  CPLDs (Complex Programmable Logic Devices) are reconfigurable digital integrated circuits used to implement custom logic functions in hardware, often for control, glue logic, and interface applications.
• F. None of above. chosen