Verilog-AMS

E820858

analog hardware description language hardware description language mixed-signal hardware description language

Verilog-AMS is a hardware description language that extends Verilog to support analog, mixed-signal, and multi-domain system modeling and simulation.

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Statements (50)

Predicate	Object
instanceOf	analog hardware description language ⓘ hardware description language ⓘ mixed-signal hardware description language ⓘ
addsFeature	analog behavioral constructs ⓘ analog event controls ⓘ analog procedural blocks ⓘ connect modules ⓘ continuous-time operators ⓘ contribution statements ⓘ discipline definitions ⓘ natures ⓘ wreal modeling support ⓘ
allows	co-simulation of analog and digital blocks ⓘ top-down design of mixed-signal systems ⓘ
basedOn	Verilog NERFINISHED ⓘ
extends	IEEE 1364 Verilog NERFINISHED ⓘ
hasComponent	analog block ⓘ digital block ⓘ discipline declaration ⓘ nature declaration ⓘ
hasSubLanguage	Verilog-A NERFINISHED ⓘ
hasSyntaxSimilarityWith	Verilog NERFINISHED ⓘ
standardizationBody	Accellera Systems Initiative NERFINISHED ⓘ
supportsAbstractionLevel	RTL-like digital GENERATED ⓘ behavioral GENERATED ⓘ mixed abstraction GENERATED ⓘ structural netlist GENERATED ⓘ
supportsDomain	analog ⓘ digital ⓘ mixed-signal ⓘ multi-domain ⓘ
supportsModeling	behavioral models ⓘ continuous-time behavior ⓘ discrete-time behavior ⓘ electrical systems ⓘ electromechanical systems ⓘ mixed-level models ⓘ structural models ⓘ
supportsSimulation	AC analysis GENERATED ⓘ DC analysis GENERATED ⓘ mixed-signal simulation GENERATED ⓘ transient analysis GENERATED ⓘ
typicalToolSupport	Cadence Spectre AMS Designer NERFINISHED ⓘ Mentor Graphics Questa ADMS NERFINISHED ⓘ Synopsys CustomSim NERFINISHED ⓘ
usedFor	analog and RF circuit modeling ⓘ behavioral modeling of analog blocks ⓘ mixed-signal integrated circuit design ⓘ system-on-chip verification ⓘ top-level mixed-signal verification ⓘ

Referenced by (1)

Full triples — surface form annotated when it differs from this entity's canonical label.

Verilog → influenced → Verilog-AMS ⓘ