MAX+PLUS II
E170426
MAX+PLUS II is a legacy computer-aided design software suite from Altera used for developing, simulating, and programming programmable logic devices such as FPGAs and CPLDs.
All labels observed (1)
| Label | Occurrences |
|---|---|
| MAX+PLUS II canonical | 2 |
How this entity was disambiguated
This entity first appeared as the object of triple T1499752 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: MAX+PLUS II Context triple: [Altera, designTool, MAX+PLUS II]
-
A.
CPLDs
CPLDs (Complex Programmable Logic Devices) are reconfigurable digital integrated circuits used to implement custom logic functions in hardware, often for control, glue logic, and interface applications.
-
B.
Altera
Altera is a semiconductor company best known for its programmable logic devices (FPGAs) and related design tools, now operating as a subsidiary of Intel.
-
C.
Lattice Semiconductor
Lattice Semiconductor is an American technology company that designs and manufactures low-power, programmable logic devices used in a wide range of electronics and embedded systems.
-
D.
PLC
The PLC is the elected legislative body of the Palestinian Authority, responsible for drafting laws and overseeing the executive in the Palestinian territories.
-
E.
IEEE 1149.4
IEEE 1149.4 is a mixed-signal test bus standard that extends JTAG boundary-scan techniques to support testing and diagnosis of analog and mixed-signal circuits on printed circuit boards.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: MAX+PLUS II Target entity description: MAX+PLUS II is a legacy computer-aided design software suite from Altera used for developing, simulating, and programming programmable logic devices such as FPGAs and CPLDs.
-
A.
CPLDs
CPLDs (Complex Programmable Logic Devices) are reconfigurable digital integrated circuits used to implement custom logic functions in hardware, often for control, glue logic, and interface applications.
-
B.
Altera
Altera is a semiconductor company best known for its programmable logic devices (FPGAs) and related design tools, now operating as a subsidiary of Intel.
-
C.
Lattice Semiconductor
Lattice Semiconductor is an American technology company that designs and manufactures low-power, programmable logic devices used in a wide range of electronics and embedded systems.
-
D.
PLC
The PLC is the elected legislative body of the Palestinian Authority, responsible for drafting laws and overseeing the executive in the Palestinian territories.
-
E.
IEEE 1149.4
IEEE 1149.4 is a mixed-signal test bus standard that extends JTAG boundary-scan techniques to support testing and diagnosis of analog and mixed-signal circuits on printed circuit boards.
- F. None of above. chosen
Statements (48)
| Predicate | Object |
|---|---|
| instanceOf |
FPGA design tool
ⓘ
computer-aided design software ⓘ electronic design automation software ⓘ |
| createdBy | Altera ⓘ |
| developer |
Altera
ⓘ
surface form:
Altera Corporation
|
| hasComponent |
fitter
ⓘ
logic simulator ⓘ programmer ⓘ schematic editor ⓘ text-based HDL editor ⓘ timing analyzer ⓘ |
| hasFeature |
constraint editor
ⓘ
graphical user interface ⓘ project management environment ⓘ waveform editor ⓘ |
| industry | electronic design automation ⓘ |
| license | proprietary software license ⓘ |
| platform |
Windows
ⓘ
surface form:
Microsoft Windows
earlier DOS-based systems ⓘ |
| provides |
device programming files
ⓘ
pin assignment tools ⓘ timing closure tools ⓘ |
| replacedBy |
Quartus design software
ⓘ
surface form:
Quartus II
|
| status | legacy software ⓘ |
| supportsDesignEntryMethod |
HDL-based design entry
ⓘ
schematic entry ⓘ state machine editor ⓘ |
| supportsDeviceType |
CPLD
ⓘ
FPGA ⓘ |
| supportsLanguage |
Altera Hardware Description Language
ⓘ
VHDL ⓘ Verilog ⓘ |
| supportsOutputFormat |
JEDEC files for CPLDs
ⓘ
programming bitstream files ⓘ |
| supportsVendorDevices | Altera programmable logic devices ⓘ |
| supportsWorkflowStage |
design entry
ⓘ
device programming ⓘ functional simulation ⓘ synthesis and fitting ⓘ timing simulation ⓘ |
| targetUser |
FPGA engineers
ⓘ
digital hardware designers ⓘ embedded system designers ⓘ |
| usedFor |
design of programmable logic devices
ⓘ
programming of programmable logic devices ⓘ simulation of programmable logic designs ⓘ |
| usedIn |
CPLD-based control logic design
ⓘ
FPGA-based prototyping ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: MAX+PLUS II Description of subject: MAX+PLUS II is a legacy computer-aided design software suite from Altera used for developing, simulating, and programming programmable logic devices such as FPGAs and CPLDs.
Referenced by (2)
Full triples — surface form annotated when it differs from this entity's canonical label.