IEEE 1364
E820857
IEEE 1364 is the IEEE standard that defines the Verilog hardware description language used for modeling and designing digital electronic systems.
All labels observed (2)
| Label | Occurrences |
|---|---|
| IEEE 1364 canonical | 1 |
| Verilog-2001 | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T9782895 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: IEEE 1364 Context triple: [Verilog, standardNumber, IEEE 1364]
-
A.
Verilog
Verilog is a hardware description language (HDL) used to model, design, and verify digital circuits and systems such as those implemented in CPLDs and FPGAs.
-
B.
VHDL
VHDL is a hardware description language used to model, simulate, and implement digital electronic systems such as FPGAs and CPLDs.
-
C.
Altera Hardware Description Language
Altera Hardware Description Language (AHDL) is a proprietary hardware description language developed by Altera for designing and implementing digital logic circuits on its programmable logic devices.
-
D.
SystemVerilog
SystemVerilog is a hardware description and verification language widely used to design, model, and verify complex digital integrated circuits and systems.
-
E.
IEEE 1149.4
IEEE 1149.4 is a mixed-signal test bus standard that extends JTAG boundary-scan techniques to support testing and diagnosis of analog and mixed-signal circuits on printed circuit boards.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: IEEE 1364 Target entity description: IEEE 1364 is the IEEE standard that defines the Verilog hardware description language used for modeling and designing digital electronic systems.
-
A.
Verilog
Verilog is a hardware description language (HDL) used to model, design, and verify digital circuits and systems such as those implemented in CPLDs and FPGAs.
-
B.
VHDL
VHDL is a hardware description language used to model, simulate, and implement digital electronic systems such as FPGAs and CPLDs.
-
C.
Altera Hardware Description Language
Altera Hardware Description Language (AHDL) is a proprietary hardware description language developed by Altera for designing and implementing digital logic circuits on its programmable logic devices.
-
D.
SystemVerilog
SystemVerilog is a hardware description and verification language widely used to design, model, and verify complex digital integrated circuits and systems.
-
E.
IEEE 1149.4
IEEE 1149.4 is a mixed-signal test bus standard that extends JTAG boundary-scan techniques to support testing and diagnosis of analog and mixed-signal circuits on printed circuit boards.
- F. None of above. chosen
Statements (45)
| Predicate | Object |
|---|---|
| instanceOf |
IEEE standard
ⓘ
hardware description language standard ⓘ |
| appliesTo |
digital logic design
ⓘ
hardware verification ⓘ testbench development ⓘ |
| competesWith | VHDL NERFINISHED ⓘ |
| defines | Verilog NERFINISHED ⓘ |
| field |
digital circuit design
ⓘ
electronic design automation ⓘ hardware design ⓘ |
| fullName | IEEE Standard for Verilog Hardware Description Language NERFINISHED ⓘ |
| governs |
Verilog concurrency model
ⓘ
Verilog simulation semantics ⓘ Verilog timing constructs ⓘ |
| hasVersion |
IEEE 1364-1995
NERFINISHED
ⓘ
IEEE 1364-2001 NERFINISHED ⓘ IEEE 1364-2005 NERFINISHED ⓘ |
| includes |
continuous assignments for Verilog
ⓘ
data types for Verilog ⓘ lexical conventions for Verilog ⓘ module definitions for Verilog ⓘ primitives for Verilog ⓘ procedural statements for Verilog ⓘ system tasks and functions for Verilog ⓘ |
| languageType | hardware description language specification ⓘ |
| publishedBy |
IEEE Standards Association
NERFINISHED
ⓘ
Institute of Electrical and Electronics Engineers NERFINISHED ⓘ |
| relatedStandard |
IEEE 1076
NERFINISHED
ⓘ
IEEE 1800 NERFINISHED ⓘ |
| relatedTo |
SystemVerilog
NERFINISHED
ⓘ
Verilog-XL NERFINISHED ⓘ |
| standardizes |
semantics of Verilog
ⓘ
simulation behavior of Verilog ⓘ syntax of Verilog ⓘ synthesis-related constructs of Verilog ⓘ |
| status | superseded in many uses by IEEE 1800 SystemVerilog ⓘ |
| usedFor |
ASIC design
ⓘ
FPGA design ⓘ behavioral modeling ⓘ gate-level modeling ⓘ modeling digital electronic systems ⓘ register-transfer level design ⓘ |
| year |
1995
ⓘ
2001 ⓘ 2005 ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: IEEE 1364 Description of subject: IEEE 1364 is the IEEE standard that defines the Verilog hardware description language used for modeling and designing digital electronic systems.
Referenced by (2)
Full triples — surface form annotated when it differs from this entity's canonical label.
this entity surface form:
Verilog-2001