IEEE 1149 family of standards

E53490

JTAG boundary-scan standard family of technical standards

The IEEE 1149 family of standards is a set of Joint Test Action Group (JTAG) boundary-scan specifications that define methods for testing, debugging, and accessing digital integrated circuits and boards.

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All labels observed (6)

Label	Occurrences
IEEE 1149.1	10
IEEE 1149 boundary-scan standards family	2
JTAG	2
IEEE 1149 family of standards canonical	1
IEEE 1149 family of test standards	1
IEEE 1149.x	1

How this entity was disambiguated

This entity first appeared as the object of triple T415890 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.

NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07

Target entity: IEEE 1149 family of standards
Context triple: [IEEE 1149.6, isPartOf, IEEE 1149 family of standards]

A. IEEE 1149.7
IEEE 1149.7 is a compact, enhanced version of the JTAG test and debug standard that reduces pin count and power while adding advanced debug and trace capabilities for modern integrated circuits.
B. IEEE 1149.1 JTAG boundary‑scan standard
The IEEE 1149.1 JTAG boundary-scan standard is a widely used test and debug specification that defines a serial interface and architecture for accessing and testing the internal logic and interconnects of integrated circuits and circuit boards.
C. IEEE 1149.6
IEEE 1149.6 is a boundary-scan test standard that extends JTAG to support structural testing of high-speed AC-coupled and differential digital interconnects on printed circuit boards.
D. IEEE Std 610.12-2010
IEEE Std 610.12-2010 is an updated IEEE standard that provides a formal glossary of terms and definitions used in software engineering.
E. IEEE 1532
IEEE 1532 is an extension of the JTAG boundary-scan standard that defines in-system programming and configuration procedures for programmable devices such as FPGAs and CPLDs.
F. None of above. chosen
G. Unsure - the case is ambiguous/there is not enough information to decide.

NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07

Target entity: IEEE 1149 family of standards
Target entity description: The IEEE 1149 family of standards is a set of Joint Test Action Group (JTAG) boundary-scan specifications that define methods for testing, debugging, and accessing digital integrated circuits and boards.

A. IEEE 1149.7
IEEE 1149.7 is a compact, enhanced version of the JTAG test and debug standard that reduces pin count and power while adding advanced debug and trace capabilities for modern integrated circuits.
B. IEEE 1149.1 JTAG boundary‑scan standard
The IEEE 1149.1 JTAG boundary-scan standard is a widely used test and debug specification that defines a serial interface and architecture for accessing and testing the internal logic and interconnects of integrated circuits and circuit boards.
C. IEEE 1149.6
IEEE 1149.6 is a boundary-scan test standard that extends JTAG to support structural testing of high-speed AC-coupled and differential digital interconnects on printed circuit boards.
D. IEEE Std 610.12-2010
IEEE Std 610.12-2010 is an updated IEEE standard that provides a formal glossary of terms and definitions used in software engineering.
E. IEEE 1532
IEEE 1532 is an extension of the JTAG boundary-scan standard that defines in-system programming and configuration procedures for programmable devices such as FPGAs and CPLDs.
F. None of above. chosen

Statements (48)

Predicate	Object
instanceOf	JTAG boundary-scan standard ⓘ family of technical standards ⓘ
acronym	IEEE 1149.1 JTAG boundary‑scan standard ⓘ surface form: JTAG
appliesTo	digital integrated circuits ⓘ printed circuit board assemblies ⓘ
basedOn	boundary-scan architecture ⓘ
communicationStyle	serial scan chain ⓘ
coreStandard	IEEE 1149 family of standards self-linksurface differs ⓘ surface form: IEEE 1149.1
defines	methods for accessing on-chip test features ⓘ methods for debugging digital systems ⓘ methods for testing digital integrated circuits ⓘ methods for testing printed circuit boards ⓘ
developedBy	Institute of Electrical and Electronics Engineers ⓘ
domain	electronic design and test ⓘ
enables	remote debugging of embedded systems ⓘ test access through a small number of pins ⓘ test of devices without physical probe access ⓘ
includes	IEEE 1149 family of standards self-linksurface differs ⓘ surface form: IEEE 1149.1 IEEE 1149.10 ⓘ IEEE 1149.10 ⓘ surface form: IEEE 1149.10 gigabit test bus standard IEEE 1149.4 ⓘ IEEE 1149.4 ⓘ surface form: IEEE 1149.4 mixed-signal test bus standard IEEE 1149.6 ⓘ IEEE 1149.6 ⓘ surface form: IEEE 1149.6 AC-coupled interconnect test standard IEEE 1149.7 ⓘ IEEE 1149.7 ⓘ surface form: IEEE 1149.7 compact JTAG standard IEEE 1149.6 ⓘ surface form: IEEE 1149.8.1 IEEE 1149.8.1 power-down test standard ⓘ
originatedFrom	Joint Test Action Group ⓘ
primaryApplication	in-system programming of devices ⓘ manufacturing test of digital boards ⓘ on-chip debug access ⓘ
relatedTo	IEEE 1500 embedded core test standard ⓘ IEEE 1532 ⓘ surface form: IEEE 1532 in-system configuration standard boundary-scan description language ⓘ
standardizedBy	IEEE Standards Association ⓘ
supports	board-level interconnect testing ⓘ device-level structural testing ⓘ non-intrusive access to device pins ⓘ test automation in production ⓘ
typicalSignals	TCK ⓘ TDI ⓘ TDO ⓘ TMS ⓘ
usesConcept	IEEE 1149.1 JTAG boundary‑scan standard ⓘ surface form: boundary-scan register instruction register ⓘ test access port ⓘ test data registers ⓘ

How these facts were elicited