IEEE 1149.10
E56156
IEEE 1149.10 is a JTAG-related IEEE standard that defines high-speed test access mechanisms for embedded instrumentation and system-level testing of complex digital devices and boards.
All labels observed (2)
| Label | Occurrences |
|---|---|
| IEEE 1149.10 canonical | 3 |
| IEEE 1149.10 gigabit test bus standard | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T415915 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: IEEE 1149.10 Context triple: [IEEE 1149.6, relatedTo, IEEE 1149.10]
-
A.
IEEE 1149.4
IEEE 1149.4 is a mixed-signal test bus standard that extends JTAG boundary-scan techniques to support testing and diagnosis of analog and mixed-signal circuits on printed circuit boards.
-
B.
IEEE 1149.7
IEEE 1149.7 is a compact, enhanced version of the JTAG test and debug standard that reduces pin count and power while adding advanced debug and trace capabilities for modern integrated circuits.
-
C.
IEEE 1149.6
IEEE 1149.6 is a boundary-scan test standard that extends JTAG to support structural testing of high-speed AC-coupled and differential digital interconnects on printed circuit boards.
-
D.
IEEE 1149 family of standards
The IEEE 1149 family of standards is a set of Joint Test Action Group (JTAG) boundary-scan specifications that define methods for testing, debugging, and accessing digital integrated circuits and boards.
-
E.
IEEE 1149.1 JTAG boundary‑scan standard
The IEEE 1149.1 JTAG boundary-scan standard is a widely used test and debug specification that defines a serial interface and architecture for accessing and testing the internal logic and interconnects of integrated circuits and circuit boards.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: IEEE 1149.10 Target entity description: IEEE 1149.10 is a JTAG-related IEEE standard that defines high-speed test access mechanisms for embedded instrumentation and system-level testing of complex digital devices and boards.
-
A.
IEEE 1149.4
IEEE 1149.4 is a mixed-signal test bus standard that extends JTAG boundary-scan techniques to support testing and diagnosis of analog and mixed-signal circuits on printed circuit boards.
-
B.
IEEE 1149.7
IEEE 1149.7 is a compact, enhanced version of the JTAG test and debug standard that reduces pin count and power while adding advanced debug and trace capabilities for modern integrated circuits.
-
C.
IEEE 1149.6
IEEE 1149.6 is a boundary-scan test standard that extends JTAG to support structural testing of high-speed AC-coupled and differential digital interconnects on printed circuit boards.
-
D.
IEEE 1149 family of standards
The IEEE 1149 family of standards is a set of Joint Test Action Group (JTAG) boundary-scan specifications that define methods for testing, debugging, and accessing digital integrated circuits and boards.
-
E.
IEEE 1149.1 JTAG boundary‑scan standard
The IEEE 1149.1 JTAG boundary-scan standard is a widely used test and debug specification that defines a serial interface and architecture for accessing and testing the internal logic and interconnects of integrated circuits and circuit boards.
- F. None of above. chosen
Statements (32)
| Predicate | Object |
|---|---|
| instanceOf |
IEEE standard
ⓘ
JTAG-related standard ⓘ |
| appliesTo |
complex digital integrated circuits
ⓘ
printed circuit boards ⓘ system-level test architectures ⓘ |
| complements |
IEEE 1149.1 JTAG boundary‑scan standard
ⓘ
surface form:
IEEE 1149.1 boundary-scan architecture
|
| defines |
high-speed test access mechanisms
ⓘ
system-level testing methods for complex digital devices and boards ⓘ test access mechanisms for embedded instrumentation ⓘ |
| domain |
boundary-scan test
ⓘ
design for testability ⓘ electronic test and measurement ⓘ |
| enables |
access to on-chip embedded instruments
ⓘ
high-speed data transfer for test and debug ⓘ |
| focusesOn |
embedded instrumentation access
ⓘ
high-speed serial test access ⓘ |
| fullName | IEEE Standard for High-Speed Test Access Port and Boundary-Scan Architecture ⓘ |
| goal |
enable scalable test access for complex systems
ⓘ
improve test access bandwidth ⓘ reduce test time for large digital systems ⓘ |
| intendedFor |
IC designers
ⓘ
board and system designers ⓘ test engineers ⓘ |
| partOfSeries |
IEEE 1149 family of standards
ⓘ
surface form:
IEEE 1149 boundary-scan standards family
|
| relatedTo |
IEEE 1149 family of standards
ⓘ
surface form:
IEEE 1149.1
IEEE 1149 family of standards ⓘ
surface form:
JTAG
|
| standardizedBy |
IEEE Standards Association
ⓘ
surface form:
IEEE
IEEE Standards Association ⓘ |
| supports |
board-level test
ⓘ
embedded test instrumentation access ⓘ system-level test ⓘ |
| uses | high-speed serial links for test access ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: IEEE 1149.10 Description of subject: IEEE 1149.10 is a JTAG-related IEEE standard that defines high-speed test access mechanisms for embedded instrumentation and system-level testing of complex digital devices and boards.
Referenced by (4)
Full triples — surface form annotated when it differs from this entity's canonical label.
this entity surface form:
IEEE 1149.10 gigabit test bus standard