IEEE 1149.10

E56156

IEEE 1149.10 is a JTAG-related IEEE standard that defines high-speed test access mechanisms for embedded instrumentation and system-level testing of complex digital devices and boards.

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Observed surface forms (1)

Surface form Occurrences
IEEE 1149.10 gigabit test bus standard 1

Statements (32)

Predicate Object
instanceOf IEEE standard
JTAG-related standard
appliesTo complex digital integrated circuits
printed circuit boards
system-level test architectures
complements IEEE 1149.1 JTAG boundary‑scan standard
surface form: IEEE 1149.1 boundary-scan architecture
defines high-speed test access mechanisms
system-level testing methods for complex digital devices and boards
test access mechanisms for embedded instrumentation
domain boundary-scan test
design for testability
electronic test and measurement
enables access to on-chip embedded instruments
high-speed data transfer for test and debug
focusesOn embedded instrumentation access
high-speed serial test access
fullName IEEE Standard for High-Speed Test Access Port and Boundary-Scan Architecture
goal enable scalable test access for complex systems
improve test access bandwidth
reduce test time for large digital systems
intendedFor IC designers
board and system designers
test engineers
partOfSeries IEEE 1149 family of standards
surface form: IEEE 1149 boundary-scan standards family
relatedTo IEEE 1149 family of standards
surface form: IEEE 1149.1

IEEE 1149 family of standards
surface form: JTAG
standardizedBy IEEE Standards Association
surface form: IEEE

IEEE Standards Association
supports board-level test
embedded test instrumentation access
system-level test
uses high-speed serial links for test access

Referenced by (3)

Full triples — surface form annotated when it differs from this entity's canonical label.

this entity surface form: IEEE 1149.10 gigabit test bus standard
IEEE 1149.6 relatedTo IEEE 1149.10