IEEE 1149.1 JTAG boundary‑scan standard

E1466

IEEE standard boundary-scan standard electronic test standard

The IEEE 1149.1 JTAG boundary-scan standard is a widely used test and debug specification that defines a serial interface and architecture for accessing and testing the internal logic and interconnects of integrated circuits and circuit boards.

Aliases (15)

IEEE 1149.1 JTAG boundary-scan standard ×54
IEEE 1149.1 ×6
JTAG ×6
IEEE 1149.1 JTAG specification ×2
EXTEST instruction ×1
IEEE 1149.1 Test Access Port ×1
IEEE 1149.1 boundary-scan ×1
IEEE 1149.1 boundary-scan architecture ×1
IEEE 1149.1 boundary-scan chains ×1
IEEE 1149.1 test access port ×1
IEEE 1149.1 test access port (TAP) ×1
IEEE Standard Test Access Port and Boundary-Scan Architecture ×1
JTAG boundary-scan ×1
TAP (Test Access Port) ×1
boundary-scan register ×1

Statements (54)

Predicate	Object
instanceOf	IEEE standard → boundary-scan standard → electronic test standard →
alsoKnownAs	IEEE 1149.1 → JTAG → JTAG boundary-scan →
appliesTo	digital integrated circuits → printed circuit boards →
architectureType	serial scan chain →
category	design for testability →
defines	IDCODE register → TAP controller → Test Access Port → boundary-scan architecture → boundary-scan register → bypass register → instruction register → serial test access port interface → test data registers →
definesOptionalSignal	TRST →
definesSignal	TCK → TDI → TDO → TMS →
field	digital integrated circuits → electronic design automation → printed circuit board testing →
fullName	IEEE Standard Test Access Port and Boundary-Scan Architecture →
hasFeature	boundary-scan cells on digital I/O pins → chaining of multiple devices in a scan path → control of output pins via scan chain → non-intrusive observation of pin states →
introducedConcept	boundary-scan cell → test access port →
publishedBy	IEEE Standards Association → Institute of Electrical and Electronics Engineers →
purpose	board-level interconnect testing → debug access to internal logic → in-system programming of devices → in-system test of integrated circuits →
relatedStandard	IEEE 1149.4 → IEEE 1149.6 → IEEE 1149.7 → IEEE 1532 →
specifies	finite state machine for TAP controller →
status	widely adopted in semiconductor industry →
supports	BYPASS instruction → EXTEST instruction → IDCODE instruction → PRELOAD instruction → SAMPLE instruction →
usedFor	field diagnostics → hardware debug → manufacturing test →

Referenced by (26)

Subject (surface form when different)	Predicate
IEEE 1149.1 JTAG boundary-scan standard ("IEEE 1149.1") → IEEE 1149.1 JTAG boundary-scan standard ("JTAG") → IEEE 1149.1 JTAG boundary-scan standard ("JTAG boundary-scan") →	alsoKnownAs
TDI ("JTAG") → TDI ("IEEE 1149.1 boundary-scan") → TMS ("JTAG") →	usedIn
IEEE 1149.4 ("IEEE 1149.1 boundary-scan chains") → IEEE 1149.7 ("IEEE 1149.1 test access port") →	compatibleWith
IEEE 1149.6 ("IEEE 1149.1") → IEEE 1532 ("IEEE 1149.1") →	extends
IEEE 1149.4 ("JTAG") → IEEE 1532 ("IEEE 1149.1") →	relatedTo
TMS ("IEEE 1149.1") → TRST ("IEEE 1149.1") →	usedInStandard
IEEE 1149 family of standards ("JTAG") →	acronym
TMS ("TAP (Test Access Port)") →	associatedWith
IEEE 1149.10 ("IEEE 1149.1 boundary-scan architecture") →	complements
TRST ("IEEE 1149.1 JTAG specification") →	definedBy
TMS ("IEEE 1149.1 JTAG specification") →	definedIn
IEEE Standards Association →	develops
IEEE 1149.1 JTAG boundary-scan standard ("IEEE Standard Test Access Port and Boundary-Scan Architecture") →	fullName
IEEE 1149.6 ("IEEE 1149.1 test access port (TAP)") →	isCompatibleWith
IEEE 1149.1 JTAG boundary-scan standard ("EXTEST instruction") →	supports
TRST ("JTAG") →	usedInInterface
IEEE 1149 family of standards ("boundary-scan register") →	usesConcept
IEEE 1532 ("IEEE 1149.1 Test Access Port") →	usesInterface