IEEE 1149.7
E10411
IEEE 1149.7 is a compact, enhanced version of the JTAG test and debug standard that reduces pin count and power while adding advanced debug and trace capabilities for modern integrated circuits.
Aliases (4)
Statements (49)
| Predicate | Object |
|---|---|
| instanceOf |
IEEE standard
→
JTAG-related standard → test and debug standard → |
| alsoKnownAs |
cJTAG
→
compact JTAG → |
| appliesTo |
complex integrated circuits
→
microcontrollers → system-on-chip devices → |
| basedOn |
JTAG
→
|
| compatibleWith |
IEEE 1149.1 test access port
→
|
| defines |
enhanced boundary-scan architecture
→
reduced-pin test access port → |
| domain |
embedded systems
→
integrated circuit test → on-chip debug → |
| extends |
IEEE 1149.1
→
|
| feature |
backward compatibility with legacy JTAG tools
→
class-based feature levels → enhanced device addressing → low-power operation modes → reduced pin interface for small packages → |
| fullName |
IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture
→
|
| goal |
add advanced debug capabilities
→
add trace capabilities → reduce JTAG pin count → reduce power consumption during test and debug → |
| relatedTo |
IEEE 1149.1
→
IEEE 1149.4 → IEEE 1149.6 → on-chip debug architectures → |
| standardizedBy |
IEEE
→
IEEE Standards Association → |
| supports |
2-pin JTAG operation
→
4-pin JTAG operation → advanced scan formats → debug access to multiple cores → hot connect and disconnect of debug tools → multi-drop topology → point-to-point topology → power management features for debug → star topology → trace data transport over JTAG pins → |
| targetEnvironment |
low-power embedded devices
→
modern integrated circuits with high pin-count constraints → |
| usedFor |
board-level test
→
in-system programming → manufacturing test → run-time debug → trace collection → |
Referenced by (7)
| Subject (surface form when different) | Predicate |
|---|---|
|
IEEE 1149.7
("compact JTAG")
→
IEEE 1149.7 ("cJTAG") → |
alsoKnownAs |
|
IEEE 1149 family of standards
→
IEEE 1149 family of standards ("IEEE 1149.7 compact JTAG standard") → |
includes |
|
IEEE 1149.7
("IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture")
→
|
fullName |
|
IEEE 1149.1 JTAG boundary-scan standard
→
|
relatedStandard |
|
IEEE 1149.6
→
|
relatedTo |