Dennard scaling

E232504

Dennard scaling is a principle in microelectronics stating that as transistors shrink, their power density stays constant, allowing higher clock speeds and more transistors per chip without increasing overall power consumption.

All labels observed (2)

Label Occurrences
Dennard scaling canonical 4
MOS transistor scaling theory 1

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Statements (47)

Predicate Object
instanceOf principle in microelectronics
scaling law
appliesTo CMOS technology
MOSFET transistors
assumes constant electric field scaling
supply voltage scales down with feature size
threshold voltage scales with device dimensions
breakdownCause leakage currents
power density constraints
voltage scaling limits
consequenceOfBreakdown greater emphasis on energy efficiency
greater emphasis on parallelism
shift toward multicore processors
thermal limits on further clock frequency increases
contrastsWith post-Dennard scaling era
coreIdea as transistors shrink, power density remains approximately constant
smaller transistors allow higher clock frequencies without increasing power density
smaller transistors allow more devices per chip at similar total power
transistor dimensions, voltage, and current scale together
describedIn “Design of ion-implanted MOSFET’s with very small physical dimensions”
enabled increasing transistor counts without proportional power increase
rapid increase in microprocessor clock speeds in the 1980s and 1990s
field computer architecture
microelectronics
semiconductor technology
hasConcept capacitance scaling
constant power density
current density scaling
delay scaling
feature size scaling
voltage scaling
historicalStatus held approximately from the 1970s to the early 2000s
implies clock frequency can increase with each technology node
higher integration density at similar power budgets
power per transistor decreases as transistors shrink
switching delay decreases with smaller transistors
influences chip power budgeting
microprocessor design trade-offs
technology node scaling strategies
namedAfter Robert H. Dennard
relatedTo Moore's law
surface form: Moore’s law
statedIn 1974
status has largely broken down in modern process nodes
supports historical CPU performance scaling
timePeriod prevalent during planar CMOS scaling era
usedBy microprocessor performance projections
semiconductor industry roadmaps

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Referenced by (5)

Full triples — surface form annotated when it differs from this entity's canonical label.

Moore's law relatedConcept Dennard scaling
“Cramming more components onto integrated circuits” relatedConcept Dennard scaling
subject surface form: Cramming more components onto integrated circuits
Carver A. Mead notableWork Dennard scaling
this entity surface form: MOS transistor scaling theory
Koomey's law relatedTo Dennard scaling
Moore 1965 paper relatedConcept Dennard scaling