RISC architecture

E220200

computer architecture instruction set architecture design philosophy

RISC architecture is a CPU design philosophy that uses a small, highly optimized set of simple instructions to achieve high performance and efficiency.

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All labels observed (6)

Label	Occurrences
RISC	12
RISC architecture canonical	2
"Reduced Instruction Set Computer" papers by Patterson and colleagues	1
Reduced Instruction Set Computer architecture	1
Reduced Instruction Set Computing	1
“The Case for the Reduced Instruction Set Computer”	1

Statements (47)

Predicate	Object
instanceOf	computer architecture ⓘ instruction set architecture design philosophy ⓘ
aimsFor	high efficiency ⓘ high performance ⓘ
benefits	easier verification of hardware ⓘ lower power consumption in many designs ⓘ reduced control complexity ⓘ
contrastsWith	CISC architecture ⓘ
designGoal	better compiler optimization ⓘ higher clock frequencies ⓘ one clock cycle per instruction for simple operations ⓘ simplified hardware ⓘ
emphasizes	fixed-length instructions ⓘ hardwired control ⓘ large register file ⓘ load-store architecture ⓘ simple addressing modes ⓘ uniform instruction format ⓘ
focusesOn	simple instructions ⓘ small instruction set ⓘ
hasFullForm	RISC architecture self-linksurface differs ⓘ surface form: Reduced Instruction Set Computer architecture
isStandardizedIn	RISC-V ⓘ surface form: RISC-V ISA specifications
isTaughtIn	computer architecture courses ⓘ
isUsedIn	ARM architecture ⓘ Alpha architecture ⓘ MIPS ⓘ surface form: MIPS architecture PowerPC ⓘ surface form: PowerPC architecture RISC-V ⓘ surface form: RISC-V architecture SPARC microprocessor architecture ⓘ surface form: SPARC architecture
originatedFrom	research on efficient instruction sets ⓘ
popularizedIn	1980s ⓘ
relatedConcept	compiler-driven optimization ⓘ instruction-level parallelism ⓘ microarchitecture design ⓘ pipeline hazards ⓘ
supports	out-of-order execution ⓘ pipelining ⓘ superscalar execution ⓘ
tradeOff	more instructions per program compared to CISC ⓘ simpler individual instructions ⓘ
typicalFeature	branch delay slots in some designs ⓘ memory access limited to load and store instructions ⓘ register-to-register arithmetic operations ⓘ separate instruction and data caches ⓘ
wasInfluencedBy	Berkeley RISC projects ⓘ surface form: Berkeley RISC project IBM 801 project ⓘ Stanford Computer Systems Laboratory ⓘ surface form: Stanford MIPS project

Referenced by (18)

Full triples — surface form annotated when it differs from this entity's canonical label.

AIM alliance → relatedConcept → RISC architecture ⓘ

MMIX → architectureStyle → RISC architecture ⓘ

this entity surface form: RISC

MMIX → relatedConcept → RISC architecture ⓘ

this entity surface form: RISC

David A. Patterson → fieldOfWork → RISC architecture ⓘ

Berkeley RISC projects → field → RISC architecture ⓘ

this entity surface form: Reduced Instruction Set Computing

Berkeley RISC projects → notablePublication → RISC architecture ⓘ

this entity surface form: "Reduced Instruction Set Computer" papers by Patterson and colleagues

Sun-4 workstation → architectureType → RISC architecture ⓘ

this entity surface form: RISC

POWER3 → instructionSetArchitecture → RISC architecture ⓘ

this entity surface form: RISC

RISC architecture → hasFullForm → RISC architecture self-linksurface differs ⓘ

this entity surface form: Reduced Instruction Set Computer architecture

AMD Radeon GCN-based GPU → architectureStyle → RISC architecture ⓘ

this entity surface form: RISC

MC88100 → design → RISC architecture ⓘ

this entity surface form: RISC

MC88110 → design → RISC architecture ⓘ

this entity surface form: RISC

RISC I → architectureFamily → RISC architecture ⓘ

this entity surface form: RISC

RISC I → publication → RISC architecture ⓘ

this entity surface form: “The Case for the Reduced Instruction Set Computer”

Acorn Archimedes → architectureType → RISC architecture ⓘ

this entity surface form: RISC

Risc PC → architecture → RISC architecture ⓘ

this entity surface form: RISC

Acorn Archimedes in 1987 → architectureType → RISC architecture ⓘ

subject surface form: Acorn Archimedes

this entity surface form: RISC

AVR microcontrollers → instructionSetType → RISC architecture ⓘ

this entity surface form: RISC