IBM 801 project
E723417
The IBM 801 project was an early experimental computer architecture effort at IBM that pioneered Reduced Instruction Set Computing (RISC) principles and strongly influenced later academic and commercial RISC designs.
All labels observed (1)
| Label | Occurrences |
|---|---|
| IBM 801 project canonical | 2 |
Statements (48)
| Predicate | Object |
|---|---|
| instanceOf |
IBM research project
ⓘ
RISC project ⓘ computer architecture research project ⓘ |
| architecturalStyle | RISC NERFINISHED ⓘ |
| basedOn | Reduced Instruction Set Computing ⓘ |
| computingModel | load-store RISC ⓘ |
| computingPlatform | experimental processor system ⓘ |
| countryOfOrigin |
United States of America
ⓘ
surface form:
United States
|
| designGoal |
enable efficient pipelining
ⓘ
maximize performance with simple instructions ⓘ shift complexity from hardware to compiler ⓘ |
| developer |
IBM
ⓘ
IBM Research NERFINISHED ⓘ |
| fieldOfWork |
compiler technology
ⓘ
instruction set architecture ⓘ microprocessor design ⓘ |
| followedBy | commercial RISC microprocessors at IBM ⓘ |
| hasPart |
IBM 801 instruction set architecture
NERFINISHED
ⓘ
IBM 801 processor NERFINISHED ⓘ |
| historicalSignificance |
influential in later RISC architectures
ⓘ
pioneered RISC principles ⓘ |
| inception | mid-1970s ⓘ |
| industry |
computer architecture
ⓘ
computer engineering ⓘ |
| influenced |
IBM POWER architecture
NERFINISHED
ⓘ
IBM POWER1 NERFINISHED ⓘ IBM ROMP NERFINISHED ⓘ IBM RS/6000 systems NERFINISHED ⓘ MIPS architecture NERFINISHED ⓘ SPARC architecture NERFINISHED ⓘ academic RISC research ⓘ commercial RISC processors ⓘ general RISC design methodology ⓘ |
| influencedBy | microprogrammed control in mainframe computers ⓘ |
| locationOfWork | IBM Thomas J. Watson Research Center NERFINISHED ⓘ |
| mainSubject |
RISC principles
ⓘ
compiler-driven architecture ⓘ instruction set design ⓘ pipeline optimization ⓘ |
| notableFor |
compiler-optimized instruction set
ⓘ
early practical RISC implementation ⓘ high performance through simplicity ⓘ large register file emphasis ⓘ load-store architecture ⓘ simple fixed-length instructions ⓘ |
| precededBy | complex instruction set mainframe designs ⓘ |
| useCase |
internal IBM applications
ⓘ
research on compiler-architecture co-design ⓘ |
Referenced by (2)
Full triples — surface form annotated when it differs from this entity's canonical label.