SH-3
E726423
SH-3 is a 32-bit member of the SuperH family of RISC microprocessor cores, designed for embedded systems and known for its compact, efficient instruction set.
All labels observed (2)
| Label | Occurrences |
|---|---|
| Hitachi SH-3 | 1 |
| SH-3 canonical | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T8286694 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: SH-3 Context triple: [SuperH, hasVersion, SH-3]
-
A.
SH-2
SH-2 is a 32-bit member of the SuperH family of RISC microprocessor cores, used in embedded systems for efficient, low-power computing.
-
B.
SH-1
SH-1 is the first-generation implementation of the SuperH 32-bit RISC microprocessor architecture developed for embedded systems.
-
C.
SH 120
SH 120 is a short state highway in Colorado that connects U.S. Route 50 to the Fremont Correctional Facility area near Penrose.
-
D.
SH 183
SH 183 is a major Texas state highway serving the Dallas–Fort Worth metropolitan area, providing an important east–west transportation corridor.
-
E.
SuperH-5 (SH-5)
SuperH-5 (SH-5) is a 32-bit RISC microprocessor core in the SuperH family, designed for embedded systems with support for advanced features like superscalar execution and DSP-style instructions.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: SH-3 Target entity description: SH-3 is a 32-bit member of the SuperH family of RISC microprocessor cores, designed for embedded systems and known for its compact, efficient instruction set.
-
A.
SH-2
SH-2 is a 32-bit member of the SuperH family of RISC microprocessor cores, used in embedded systems for efficient, low-power computing.
-
B.
SH-1
SH-1 is the first-generation implementation of the SuperH 32-bit RISC microprocessor architecture developed for embedded systems.
-
C.
SH 120
SH 120 is a short state highway in Colorado that connects U.S. Route 50 to the Fremont Correctional Facility area near Penrose.
-
D.
SH 183
SH 183 is a major Texas state highway serving the Dallas–Fort Worth metropolitan area, providing an important east–west transportation corridor.
-
E.
SuperH-5 (SH-5)
SuperH-5 (SH-5) is a 32-bit RISC microprocessor core in the SuperH family, designed for embedded systems with support for advanced features like superscalar execution and DSP-style instructions.
- F. None of above. chosen
Statements (45)
| Predicate | Object |
|---|---|
| instanceOf |
SuperH architecture core
ⓘ
microprocessor core ⓘ |
| addressSpace | 32-bit address space ⓘ |
| architectureFamily | SuperH NERFINISHED ⓘ |
| belongsTo | embedded RISC CPU cores ⓘ |
| bitWidth | 32-bit ⓘ |
| compatibleWith | SuperH toolchains ⓘ |
| designedBy | Hitachi NERFINISHED ⓘ |
| designedFor | embedded systems ⓘ |
| developedBy | Hitachi NERFINISHED ⓘ |
| hasAddressBusWidth | 32-bit address bus ⓘ |
| hasDataPathWidth | 32-bit data path ⓘ |
| hasFeature |
compact code density
ⓘ
exception handling ⓘ fixed-length 16-bit instructions ⓘ low power consumption ⓘ on-chip peripherals support ⓘ support for real-time applications ⓘ |
| hasPipelineType | RISC pipeline ⓘ |
| instructionSetArchitecture | SuperH ISA NERFINISHED ⓘ |
| introducedAs | 32-bit extension of earlier SuperH cores ⓘ |
| isPartOf | SuperH processor family NERFINISHED ⓘ |
| isSuccessorOf | SH-2 ⓘ |
| knownFor |
compact instruction set
ⓘ
efficient instruction set ⓘ |
| laterProducedBy | Renesas Technology NERFINISHED ⓘ |
| optimizedFor |
code density
ⓘ
embedded performance ⓘ |
| processorArchitectureType | RISC NERFINISHED ⓘ |
| registerWidth | 32 bits ⓘ |
| supports |
interrupt handling
ⓘ
little-endian mode ⓘ memory management unit ⓘ on-chip cache memory ⓘ power management features ⓘ |
| supportsProgrammingLanguage |
C
NERFINISHED
ⓘ
C++ NERFINISHED ⓘ |
| targetMarket |
embedded microcontrollers
ⓘ
system-on-chip designs ⓘ |
| usedAs | CPU core in SoC devices ⓘ |
| usedIn |
consumer electronics
ⓘ
embedded controllers ⓘ handheld devices ⓘ industrial control systems ⓘ |
| wordLength | 32 bits ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: SH-3 Description of subject: SH-3 is a 32-bit member of the SuperH family of RISC microprocessor cores, designed for embedded systems and known for its compact, efficient instruction set.
Referenced by (2)
Full triples — surface form annotated when it differs from this entity's canonical label.
this entity surface form:
Hitachi SH-3