SH-3

E726423

SH-3 is a 32-bit member of the SuperH family of RISC microprocessor cores, designed for embedded systems and known for its compact, efficient instruction set.

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Observed surface forms (1)

Surface form Occurrences
Hitachi SH-3 1

Statements (45)

Predicate Object
instanceOf SuperH architecture core
microprocessor core
addressSpace 32-bit address space
architectureFamily SuperH NERFINISHED
belongsTo embedded RISC CPU cores
bitWidth 32-bit
compatibleWith SuperH toolchains
designedBy Hitachi NERFINISHED
designedFor embedded systems
developedBy Hitachi NERFINISHED
hasAddressBusWidth 32-bit address bus
hasDataPathWidth 32-bit data path
hasFeature compact code density
exception handling
fixed-length 16-bit instructions
low power consumption
on-chip peripherals support
support for real-time applications
hasPipelineType RISC pipeline
instructionSetArchitecture SuperH ISA NERFINISHED
introducedAs 32-bit extension of earlier SuperH cores
isPartOf SuperH processor family NERFINISHED
isSuccessorOf SH-2
knownFor compact instruction set
efficient instruction set
laterProducedBy Renesas Technology NERFINISHED
optimizedFor code density
embedded performance
processorArchitectureType RISC NERFINISHED
registerWidth 32 bits
supports interrupt handling
little-endian mode
memory management unit
on-chip cache memory
power management features
supportsProgrammingLanguage C NERFINISHED
C++ NERFINISHED
targetMarket embedded microcontrollers
system-on-chip designs
usedAs CPU core in SoC devices
usedIn consumer electronics
embedded controllers
handheld devices
industrial control systems
wordLength 32 bits

Referenced by (2)

Full triples — surface form annotated when it differs from this entity's canonical label.

SuperH hasVersion SH-3
Hitachi SH-4 predecessor SH-3
this entity surface form: Hitachi SH-3