Triple

T8286694
Position Surface form Disambiguated ID Type / Status
Subject SuperH E193802 entity
Predicate hasVersion P455 FINISHED
Object SH-3
SH-3 is a 32-bit member of the SuperH family of RISC microprocessor cores, designed for embedded systems and known for its compact, efficient instruction set.
 E726423 NE FINISHED

How this triple was built (4 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: SH-3 | Statement: [SuperH, hasVersion, SH-3]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07 
Target entity: SH-3
Context triple: [SuperH, hasVersion, SH-3]
  • A. SH-2
    SH-2 is a 32-bit member of the SuperH family of RISC microprocessor cores, used in embedded systems for efficient, low-power computing.
  • B. SH-1
    SH-1 is the first-generation implementation of the SuperH 32-bit RISC microprocessor architecture developed for embedded systems.
  • C. SH 120
    SH 120 is a short state highway in Colorado that connects U.S. Route 50 to the Fremont Correctional Facility area near Penrose.
  • D. SH 183
    SH 183 is a major Texas state highway serving the Dallas–Fort Worth metropolitan area, providing an important east–west transportation corridor.
  • E. SuperH-5 (SH-5)
    SuperH-5 (SH-5) is a 32-bit RISC microprocessor core in the SuperH family, designed for embedded systems with support for advanced features like superscalar execution and DSP-style instructions.
  • F. None of above. chosen
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg Description generation gpt-5.1
Instruction
Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: SH-3
Triple: [SuperH, hasVersion, SH-3]
Generated description
SH-3 is a 32-bit member of the SuperH family of RISC microprocessor cores, designed for embedded systems and known for its compact, efficient instruction set.
NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07 
Target entity: SH-3
Target entity description: SH-3 is a 32-bit member of the SuperH family of RISC microprocessor cores, designed for embedded systems and known for its compact, efficient instruction set.
  • A. SH-2
    SH-2 is a 32-bit member of the SuperH family of RISC microprocessor cores, used in embedded systems for efficient, low-power computing.
  • B. SH-1
    SH-1 is the first-generation implementation of the SuperH 32-bit RISC microprocessor architecture developed for embedded systems.
  • C. SH 120
    SH 120 is a short state highway in Colorado that connects U.S. Route 50 to the Fremont Correctional Facility area near Penrose.
  • D. SH 183
    SH 183 is a major Texas state highway serving the Dallas–Fort Worth metropolitan area, providing an important east–west transportation corridor.
  • E. SuperH-5 (SH-5)
    SuperH-5 (SH-5) is a 32-bit RISC microprocessor core in the SuperH family, designed for embedded systems with support for advanced features like superscalar execution and DSP-style instructions.
  • F. None of above. chosen

Provenance (5 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69ca82e32db481908b72f3804fa71152 completed March 30, 2026, 2:04 p.m.
NER Named-entity recognition batch_69cb7ad3722481908076508908d18621 completed March 31, 2026, 7:42 a.m.
NED1 Entity disambiguation (via context triple) batch_69cd952399dc8190914951d4e9e36c38 completed April 1, 2026, 9:58 p.m.
NEDg Description generation batch_69cdab59ac188190ac017651b5a9a04a completed April 1, 2026, 11:33 p.m.
NED2 Entity disambiguation (via description) batch_69cdb2ae376c8190b3918ba6b269dba9 completed April 2, 2026, 12:05 a.m.
Created at: March 30, 2026, 5:52 p.m.