Triple

T28771517
Position Surface form Disambiguated ID Type / Status
Subject SH-3 E726423 entity
Predicate hasAddressBusWidth P178344 FINISHED
Object 32-bit address bus LITERAL FINISHED

How this triple was built (2 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: 32-bit address bus | Statement: [SH-3, hasAddressBusWidth, 32-bit address bus]
PD Predicate disambiguation gpt-5-mini-2025-08-07
Target predicate: hasAddressBusWidth
Context triple: [SH-3, hasAddressBusWidth, 32-bit address bus]
  • A. memoryBusWidthBits chosen
    Indicates the width, in bits, of the data path used by the memory bus to transfer information.
  • B. supportsMemoryBusWidth
    Indicates that one entity is compatible with or able to operate using the specified memory bus width of another entity.
  • C. busWidthComparedToISA
    Indicates how the width of a bus compares to the width defined by a given instruction set architecture (ISA), such as being wider, narrower, or equal.
  • D. supportsByteAddressing
    Indicates that one entity provides the capability for direct access to individual bytes within its addressable memory or data space for another entity.
  • E. hasBusArchitecture
    Indicates that one entity uses, implements, or is characterized by a particular bus architecture in its design or operation.
  • F. None of above.

Provenance (3 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69f03199997c8190b6ae43fb19312443 completed April 28, 2026, 4:03 a.m.
NER Named-entity recognition batch_69f74c70fd248190a9d5543afcb08211 completed May 3, 2026, 1:24 p.m.
PD Predicate disambiguation batch_69f7478e3b548190a51d5d436e2bb036 completed May 3, 2026, 1:03 p.m.
Created at: April 28, 2026, 6:16 a.m.