Triple
T28771476
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | SH-3 |
E726423
|
entity |
| Predicate | instanceOf |
P0
|
FINISHED |
| Object | SuperH architecture core |
C54317
|
CONCEPT FINISHED |
How this triple was built (1 step)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
CD
Concept disambiguation
gpt-5-mini-2025-08-07
Target class: SuperH architecture core Context triple: [SH-3, instanceOf, SuperH architecture core]
-
A.
SuperH architecture
SuperH architecture is a family of 32-bit RISC microprocessor architectures developed by Hitachi (later Renesas) for embedded systems, emphasizing compact instruction encoding and low power consumption.
-
B.
SuperH-compatible CPU core
chosen
A SuperH-compatible CPU core is a processor design that implements the SuperH instruction set architecture, enabling binary compatibility with existing SuperH software while potentially offering custom performance, power, or integration enhancements.
-
C.
SuperH architecture family member
A SuperH architecture family member is a specific processor design within the SuperH RISC microcontroller and microprocessor family, sharing the core instruction set principles while differing in features, performance, and intended applications.
-
D.
Super Nintendo Entertainment System enhancement chip
A Super Nintendo Entertainment System enhancement chip is a specialized coprocessor embedded in or alongside SNES game cartridges to extend the console’s native capabilities, such as graphics, sound, or processing power, for specific titles.
-
E.
Motorola 88000 family microprocessor
The Motorola 88000 family microprocessor is a series of 32-bit RISC CPUs developed by Motorola in the late 1980s, designed for high-performance computing and embedded systems with a clean, load-store architecture.
- F. None of above.
Provenance (1 batch)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69f03199997c8190b6ae43fb19312443 |
completed | April 28, 2026, 4:03 a.m. |
Created at: April 28, 2026, 6:16 a.m.