Disambiguation evidence for IEEE 1149.1 JTAG boundary‑scan standard via surface form
"IEEE 1149.1 JTAG boundary-scan standard"
As subject (54)
Triples where this entity appears as subject under the
label "IEEE 1149.1 JTAG boundary-scan standard".
| Predicate | Object |
|---|---|
| alsoKnownAs |
IEEE 1149.1 JTAG boundary‑scan standard
ⓘ
surface form:
IEEE 1149.1
|
| alsoKnownAs |
IEEE 1149.1 JTAG boundary‑scan standard
ⓘ
surface form:
JTAG
|
| alsoKnownAs |
IEEE 1149.1 JTAG boundary‑scan standard
ⓘ
surface form:
JTAG boundary-scan
|
| appliesTo | digital integrated circuits ⓘ |
| appliesTo | printed circuit boards ⓘ |
| architectureType | serial scan chain ⓘ |
| category | design for testability ⓘ |
| defines | IDCODE register ⓘ |
| defines | TAP controller ⓘ |
| defines | Test Access Port ⓘ |
| defines | boundary-scan architecture ⓘ |
| defines | boundary-scan register ⓘ |
| defines | bypass register ⓘ |
| defines | instruction register ⓘ |
| defines | serial test access port interface ⓘ |
| defines | test data registers ⓘ |
| definesOptionalSignal | TRST ⓘ |
| definesSignal | TCK ⓘ |
| definesSignal | TDI ⓘ |
| definesSignal | TDO ⓘ |
| definesSignal | TMS ⓘ |
| field | digital integrated circuits ⓘ |
| field | electronic design automation ⓘ |
| field | printed circuit board testing ⓘ |
| fullName |
IEEE 1149.1 JTAG boundary‑scan standard
self-linksurface differs
ⓘ
surface form:
IEEE Standard Test Access Port and Boundary-Scan Architecture
|
| hasFeature | boundary-scan cells on digital I/O pins ⓘ |
| hasFeature | chaining of multiple devices in a scan path ⓘ |
| hasFeature | control of output pins via scan chain ⓘ |
| hasFeature | non-intrusive observation of pin states ⓘ |
| instanceOf | IEEE standard ⓘ |
| instanceOf | boundary-scan standard ⓘ |
| instanceOf | electronic test standard ⓘ |
| introducedConcept | boundary-scan cell ⓘ |
| introducedConcept | test access port ⓘ |
| publishedBy | IEEE Standards Association ⓘ |
| publishedBy | Institute of Electrical and Electronics Engineers ⓘ |
| purpose | board-level interconnect testing ⓘ |
| purpose | debug access to internal logic ⓘ |
| purpose | in-system programming of devices ⓘ |
| purpose | in-system test of integrated circuits ⓘ |
| relatedStandard |
IEEE 1149.6
ⓘ
surface form:
IEEE 1149.4
|
| relatedStandard | IEEE 1149.6 ⓘ |
| relatedStandard | IEEE 1149.7 ⓘ |
| relatedStandard | IEEE 1532 ⓘ |
| specifies | finite state machine for TAP controller ⓘ |
| status | widely adopted in semiconductor industry ⓘ |
| supports | BYPASS instruction ⓘ |
| supports |
IEEE 1149.1 JTAG boundary‑scan standard
self-linksurface differs
ⓘ
surface form:
EXTEST instruction
|
| supports | IDCODE instruction ⓘ |
| supports | PRELOAD instruction ⓘ |
| supports | SAMPLE instruction ⓘ |
| usedFor | field diagnostics ⓘ |
| usedFor | hardware debug ⓘ |
| usedFor | manufacturing test ⓘ |