instruction set architecture extension
C8848
concept
An instruction set architecture extension is an addition of new machine-level instructions or capabilities to an existing ISA to enhance performance, functionality, or support for specialized workloads while maintaining compatibility with the base architecture.
All labels observed (29)
| Label | Occurrences |
|---|---|
| instruction set extension | 14 |
| instruction set architecture extension canonical | 7 |
| ARM architecture extension | 3 |
| x86 extension | 3 |
| ARM architecture revision | 2 |
| RISC-V ISA extension | 2 |
| ARM architecture feature | 1 |
| ARM architecture profile | 1 |
| ARM architecture version | 1 |
| ARMv8 instruction | 1 |
| CPU instruction | 1 |
| CPU instruction set extension | 1 |
| CPU instruction set feature | 1 |
| Intel AES-NI instruction | 1 |
| Intel CPU instruction | 1 |
| Intel processor extension | 1 |
| MIPS architecture feature | 1 |
| RISC-V bit-manipulation subextension | 1 |
| RISC-V instruction set extension | 1 |
| RISC-V standard extension | 1 |
| SHA-256 acceleration instruction | 1 |
| bit-manipulation subextension | 1 |
| cryptographic extension instruction | 1 |
| fused multiply-add instruction set | 1 |
| hardware instruction set extension | 1 |
| hardware-based memory protection extension | 1 |
| reduced instruction set computing extension | 1 |
| transactional memory extension | 1 |
| x86 instruction | 1 |
Instances (40)
| Instance | Via concept surface |
|---|---|
| Intel VT-x | CPU instruction set extension |
| Intel 64 | — |
| Intel AVX | instruction set extension |
| Intel AES-NI | instruction set extension |
| SSE2 | instruction set extension |
| SSE3 | instruction set extension |
| Intel AVX2 | instruction set extension |
| A (atomic instructions) | RISC-V standard extension |
| B (bit-manipulation extension) | RISC-V ISA extension |
| P (packed-SIMD extension) | RISC-V instruction set extension |
| NEON SIMD | ARM architecture extension |
| ARMv8 cryptographic extensions | instruction set extension |
| Vector Multimedia Extension | — |
| ARMv9-A | ARM architecture profile |
| Thumb instruction set | reduced instruction set computing extension |
| ARMv6 architecture family | ARM architecture version |
| VMX | — |
|
Intel Secure Key (RDRAND)
surface form:
Intel Secure Key
|
CPU instruction set feature |
| RDSEED | x86 instruction |
| Intel MPX | hardware-based memory protection extension |
| SSE | instruction set extension |
| Intel TSX-NI | hardware instruction set extension |
| AVX | instruction set extension |
| 3DNow! | instruction set extension |
| MMX | instruction set extension |
| FMA3 | fused multiply-add instruction set |
| Extended Memory 64 Technology | — |
| AESENCLAST | CPU instruction |
| Intel SHA Extensions | instruction set extension |
| SSE4.2 | instruction set extension |
| TrustZone security extension | ARM architecture extension |
| VFP floating-point extension | ARM architecture extension |
| Zbr (bit matrix operations) | RISC-V ISA extension |
| Zbt (ternary bit-manipulation) | bit-manipulation subextension |
| MIPS SIMD extensions | instruction set extension |
| ARMv8.1-M | ARM architecture revision |
| ARM SVE | — |
| SHA256SU0 | ARMv8 instruction |
| ARMv8.2-M | ARM architecture revision |
| Streaming SIMD Extensions | instruction set extension |