SHA256SU0
E732965
SHA256SU0 is an ARMv8 cryptographic extension instruction used to accelerate part of the SHA-256 message schedule computation in hardware.
Statements (26)
| Predicate | Object |
|---|---|
| instanceOf |
ARMv8 instruction
ⓘ
SHA-256 acceleration instruction ⓘ cryptographic extension instruction ⓘ |
| algorithm | SHA-256 NERFINISHED ⓘ |
| architecture |
AArch32
NERFINISHED
ⓘ
AArch64 NERFINISHED ⓘ ARMv8-A NERFINISHED ⓘ |
| availability | ARMv8 processors with cryptographic extensions enabled ⓘ |
| belongsToExtension | ARMv8 Cryptography Extensions NERFINISHED ⓘ |
| category | SIMD and cryptographic instruction ⓘ |
| effect |
improves SHA-256 throughput on ARMv8 processors
ⓘ
reduces number of instructions needed for SHA-256 schedule ⓘ |
| executionDomain | integer and SIMD pipeline ⓘ |
| introducedBy | ARM NERFINISHED ⓘ |
| opcodeClass | SHA-256 schedule update instruction ⓘ |
| operatesOn |
32-bit words
ⓘ
vector registers ⓘ |
| purpose | accelerate part of SHA-256 message schedule ⓘ |
| relatedTo |
SHA256H
ⓘ
SHA256H2 ⓘ SHA256SU1 ⓘ |
| standardizedIn | ARMv8-A architecture specification NERFINISHED ⓘ |
| usedFor |
SHA-256 message schedule computation
ⓘ
hardware acceleration of SHA-256 ⓘ |
| usedIn |
cryptographic libraries targeting ARMv8
ⓘ
optimized SHA-256 software implementations ⓘ |
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.