AESENCLAST
E653452
AESENCLAST is an Intel AES-NI hardware instruction that performs the final round of AES encryption on a data block to accelerate cryptographic operations.
Statements (47)
| Predicate | Object |
|---|---|
| instanceOf |
CPU instruction
ⓘ
Intel AES-NI instruction ⓘ |
| appliesTo |
AES-128
NERFINISHED
ⓘ
AES-192 NERFINISHED ⓘ AES-256 NERFINISHED ⓘ |
| architecture |
x86
ⓘ
x86-64 ⓘ |
| availability |
Intel processors with AES-NI support
ⓘ
some AMD processors supporting AES-NI ⓘ |
| belongsToExtension | AES-NI NERFINISHED ⓘ |
| benefit |
improved cryptographic throughput
ⓘ
lower power consumption for AES workloads ⓘ reduced CPU cycles for AES encryption ⓘ |
| category | SIMD instruction ⓘ |
| dataBlockSize | 128-bit ⓘ |
| domain |
computer architecture
ⓘ
cryptography ⓘ |
| effectOnFlags | does not modify EFLAGS ⓘ |
| encodingForm | SSE instruction encoding ⓘ |
| inputOperandType | XMM register ⓘ |
| intrinsicName | _mm_aesenclast_si128 (Intel C intrinsics) ⓘ |
| introducedBy | Intel NERFINISHED ⓘ |
| operandCount | 2 ⓘ |
| operandRole |
one destination operand
ⓘ
one source operand ⓘ |
| operationType | AES encryption final round ⓘ |
| outputOperandType | XMM register ⓘ |
| purpose |
accelerate AES encryption
ⓘ
hardware-accelerated cryptography ⓘ |
| relatedInstruction |
AESDEC
ⓘ
AESDECLAST ⓘ AESENC ⓘ AESENCLAST ⓘ AESIMC ⓘ AESKEYGENASSIST NERFINISHED ⓘ |
| roundType | final AES round ⓘ |
| securityImpact | mitigates timing side-channel attacks compared to software AES ⓘ |
| standardizedIn | Intel 64 and IA-32 Architectures Software Developer’s Manual NERFINISHED ⓘ |
| status | active ⓘ |
| usedBy |
compilers with AES intrinsics
ⓘ
hand-optimized assembly implementations of AES ⓘ |
| usedIn |
AES encryption routines
ⓘ
TLS implementations ⓘ cryptographic libraries ⓘ disk encryption software ⓘ |
| usesExecutionUnit | AES-NI hardware unit ⓘ |
| usesKeySchedule | yes ⓘ |
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.