ARMv5 architecture

E358144
32-bit RISC architecture ARM architecture family member instruction set architecture

ARMv5 architecture is a 32-bit RISC processor architecture from ARM that introduced enhancements over earlier ARM generations, including support for more advanced instruction sets and extensions used in many embedded and mobile devices.

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All labels observed (6)

Label Occurrences
ARMv5 architecture family 2
ARMv5 1
ARMv5 architecture canonical 1

Statements (49)

Predicate Object
instanceOf 32-bit RISC architecture ⓘ
ARM architecture family member ⓘ
instruction set architecture ⓘ
addressSpace 32-bit linear address space ⓘ
addsFeature DSP-enhanced instruction set (E extension) ⓘ
Jazelle Java bytecode execution (J extension) ⓘ
enhanced multiply and multiply-accumulate operations ⓘ
improved exception handling ⓘ
saturating arithmetic for DSP ⓘ
addsOver ARMv4 ⓘ
surface form: ARMv4T
architectureStyle RISC ⓘ
backwardCompatibleWith ARMv4 ⓘ
surface form: ARMv4T
bitWidth 32-bit ⓘ
codeDensity improved via Thumb support ⓘ
developer Arm Ltd. ⓘ
surface form: ARM Limited
endianSupport bi-endian ⓘ
little-endian ⓘ
includesVersion ARMv5 architecture self-linksurface differs ⓘ
surface form: ARMv5T

ARMv5 architecture self-linksurface differs ⓘ
surface form: ARMv5TE

ARMv5 architecture self-linksurface differs ⓘ
surface form: ARMv5TEJ
introduced late 1990s ⓘ
marketRole mainstream embedded architecture in early 2000s ⓘ
powerEfficiency optimized for low power consumption ⓘ
predecessor ARMv4 ⓘ
registerFile 16 general-purpose registers (architected) ⓘ
successor ARMv6 architecture family ⓘ
surface form: ARMv6
supports ARM ⓘ
surface form: ARM instruction set

Jazelle DBX ⓘ
Thumb instruction set ⓘ
clz (count leading zeros) instruction ⓘ
conditional execution of most instructions ⓘ
enhanced DSP instructions ⓘ
enhanced multiply-accumulate instructions ⓘ
saturating arithmetic instructions ⓘ
supportsOperatingSystem Linux ⓘ
Windows Embedded family ⓘ
surface form: Windows CE

various real-time operating systems ⓘ
targetDomain consumer electronics ⓘ
embedded systems ⓘ
mobile devices ⓘ
networking equipment ⓘ
usedIn ARM10 processor family ⓘ
ARM9 ⓘ
surface form: ARM9 processor family

Intel XScale ⓘ
surface form: XScale processors

many system-on-chip designs ⓘ
uses 16-bit Thumb instruction encoding ⓘ
fixed 32-bit ARM instruction encoding ⓘ
load-store architecture ⓘ
wordSize 32 bits ⓘ

Referenced by (7)

Full triples — surface form annotated when it differs from this entity's canonical label.

VFP floating-point extension → targetPlatform → ARMv5 architecture ⓘ
ARMv6 architecture family → predecessor → ARMv5 architecture ⓘ
this entity surface form: ARMv5 architecture family
ARMv6 architecture family → backwardCompatibleWith → ARMv5 architecture ⓘ
this entity surface form: ARMv5 architecture family
RISC OS → architecture → ARMv5 architecture ⓘ
this entity surface form: ARMv5
ARMv5 architecture → includesVersion → ARMv5 architecture self-linksurface differs ⓘ
subject surface form: ARMv5
this entity surface form: ARMv5T
ARMv5 architecture → includesVersion → ARMv5 architecture self-linksurface differs ⓘ
subject surface form: ARMv5
this entity surface form: ARMv5TE
ARMv5 architecture → includesVersion → ARMv5 architecture self-linksurface differs ⓘ
subject surface form: ARMv5
this entity surface form: ARMv5TEJ