Harvard architecture
E87766
Harvard architecture is a computer architecture design that uses separate memory and signal pathways for instructions and data, enabling simultaneous access and often improved performance over unified-memory designs.
Aliases (2)
Statements (48)
| Predicate | Object |
|---|---|
| instanceOf |
computer architecture
→
instruction set architecture concept → |
| aimsTo |
improve performance over unified-memory designs
→
|
| canBeImplementedAs |
modified Harvard architecture
→
strict Harvard architecture → |
| canImprove |
throughput of pipelined processors
→
|
| canReduce |
instruction fetch bottlenecks
→
|
| contrastsWith |
Princeton architecture
→
von Neumann architecture → |
| differsFrom |
von Neumann architecture in bus structure
→
von Neumann architecture in memory organization → |
| emergedIn |
1940s
→
|
| enables |
simultaneous access to instructions and data
→
|
| hasAlternativeName |
Harvard computer architecture
→
|
| hasLimitation |
more complex memory design than unified-memory systems
→
more complex programming model for self-modifying code → requires explicit mechanisms to write to instruction memory → |
| hasProperty |
can allow different access times for instructions and data
→
can allow different memory technologies for code and data → can allow different word widths for instructions and data → can fetch instructions and data in parallel → can simplify pipeline design → physically separate instruction and data memories → reduces contention between instruction fetch and data access → separate instruction and data buses → |
| historicallyAssociatedWith |
Harvard Mark I computer
→
|
| influenced |
modified Harvard architecture
→
|
| isBasisFor |
modified Harvard architecture
→
|
| isCharacterizedBy |
no single shared bus for instructions and data
→
no single shared memory for instructions and data → |
| isCommonIn |
AVR microcontrollers
→
PIC microcontrollers → many DSP chips → |
| isDiscussedIn |
computer architecture textbooks
→
|
| isNamedAfter |
Harvard University
NERFINISHED
→
|
| isTaughtIn |
computer engineering curricula
→
computer science curricula → |
| isUsedIn |
digital signal processors
→
embedded systems → microcontrollers → some DSP-oriented CPUs → some RISC microcontrollers → |
| originatedAt |
Harvard University
NERFINISHED
→
|
| supports |
parallel instruction fetch and data access
→
|
| uses |
separate memory for data
→
separate memory for instructions → separate signal pathways for data → separate signal pathways for instructions → |
Referenced by (3)
| Subject (surface form when different) | Predicate |
|---|---|
|
Computer Command System
("non–von Neumann architecture")
→
|
architecture |
|
von Neumann architecture
→
|
contrastedWith |
|
Harvard architecture
("Harvard computer architecture")
→
|
hasAlternativeName |