MIPS III

E726418

MIPS III is a 64-bit RISC instruction set architecture in the MIPS family, extending earlier versions with larger address space and enhanced computational capabilities.

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Statements (45)

Predicate Object
instanceOf MIPS architecture version
instruction set architecture
addressSpaceSize 64-bit virtual address space
addsFeature 64-bit general-purpose registers compared to MIPS II
enhanced exception handling for 64-bit mode
extended virtual address space compared to MIPS II
applicationDomain embedded systems
servers
workstations
architectureFamily MIPS NERFINISHED
backwardCompatibleWith MIPS I NERFINISHED
MIPS II NERFINISHED
bitWidth 64-bit
coprocessorModel CP0 system control coprocessor
CP1 floating-point coprocessor NERFINISHED
designedBy MIPS Technologies NERFINISHED
endianness bi-endian
extends MIPS II instruction set NERFINISHED
instructionLength fixed 32-bit instructions
instructionSetType RISC NERFINISHED
introducedFor high-performance 64-bit systems
mode 32-bit compatibility mode
64-bit operation mode
pipelineModel scalar pipelined RISC
predecessor MIPS II NERFINISHED
registerWidth 64-bit general-purpose registers
standardizedAs part of MIPS32/MIPS64 architectural lineage
successor MIPS IV NERFINISHED
MIPS64 NERFINISHED
supports 64-bit addressing
64-bit integer arithmetic
64-bit load and store operations
atomic operations via load-linked/store-conditional
delayed branches
floating-point operations via coprocessor 1
integer multiply and divide instructions
load delay slots (in some implementations)
memory management unit operations
virtual memory
usedIn MIPS R4000 family NERFINISHED
MIPS R4400 NERFINISHED
MIPS R4600 NERFINISHED
MIPS R4700 NERFINISHED
MIPS R5000 NERFINISHED
wordSize 32-bit word instructions

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