Triple
T8284548
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Microprocessor without Interlocked Pipeline Stages |
E193757
|
entity |
| Predicate | hasVariant |
P455
|
FINISHED |
| Object |
MIPS III
MIPS III is a 64-bit RISC instruction set architecture in the MIPS family, extending earlier versions with larger address space and enhanced computational capabilities.
|
E726418
|
NE FINISHED |
Provenance (5 batches)
| Stage | Batch ID | Job type | Status |
|---|---|---|---|
| creating | batch_69ca82e217a48190880695635c44b2ed |
elicitation | completed |
| NER | batch_69cb7ad0535081908bb234cfc0e32b32 |
ner | completed |
| NED1 | batch_69cd952399dc8190914951d4e9e36c38 |
ned_source_triple | completed |
| NED2 | batch_69cdb2ae376c8190b3918ba6b269dba9 |
ned_description | completed |
| NEDg | batch_69cdab59ac188190ac017651b5a9a04a |
nedg | completed |
Created at: March 30, 2026, 5:52 p.m.