AVX-512

E640424

SIMD instruction set vector instruction set

AVX-512 is an advanced SIMD instruction set for x86 processors that enables high-throughput parallel processing using 512-bit wide vector operations.

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Observed surface forms (2)

Surface form	Occurrences
Intel AVX-512	3
Intel AVX-512 instruction set	1

Statements (72)

Predicate	Object
instanceOf	SIMD instruction set ⓘ vector instruction set ⓘ
architectureFamily	x86 NERFINISHED ⓘ
backwardCompatibleWith	AVX2 at instruction-set level ⓘ
bitWidth	512-bit ⓘ
comparedTo	AVX2 NERFINISHED ⓘ
detectableVia	CPUID instruction ⓘ
enables	high-throughput parallel processing ⓘ processing of 16 32-bit integers per vector ⓘ processing of 16 single-precision floats per vector ⓘ processing of 32 16-bit integers per vector ⓘ processing of 64 8-bit integers per vector ⓘ processing of 8 64-bit integers per vector ⓘ processing of 8 double-precision floats per vector ⓘ
extends	AVX NERFINISHED ⓘ AVX2 NERFINISHED ⓘ SSE NERFINISHED ⓘ
firstIntroducedInMicroarchitecture	Intel Knights Landing NERFINISHED ⓘ Intel Skylake-X NERFINISHED ⓘ
introducedBy	Intel NERFINISHED ⓘ
mayBeDisabledBy	BIOS settings ⓘ
mayBeDisabledBy	microcode updates ⓘ
opmaskRegisterCount	8 ⓘ
opmaskRegisterWidth	64-bit ⓘ
optimizationConcern	higher power consumption ⓘ thermal throttling risk ⓘ
provides	mask-based predication not in AVX2 ⓘ more registers than AVX2 ⓘ wider vectors than AVX2 ⓘ
registerWidth	512-bit ZMM registers ⓘ
requires	hardware support in CPU ⓘ
subset	AVX-5124FMAPS NERFINISHED ⓘ AVX-5124VNNIW ⓘ AVX-512BF16 NERFINISHED ⓘ AVX-512BITALG NERFINISHED ⓘ AVX-512BW ⓘ AVX-512DQ ⓘ AVX-512ER NERFINISHED ⓘ AVX-512F NERFINISHED ⓘ AVX-512IFMA NERFINISHED ⓘ AVX-512PF NERFINISHED ⓘ AVX-512VBMI NERFINISHED ⓘ AVX-512VL NERFINISHED ⓘ AVX-512VNNI NERFINISHED ⓘ AVX-512VP2INTERSECT ⓘ
subset	AVX-512CD NERFINISHED ⓘ
supports	bitwise operations ⓘ conflict detection instructions ⓘ expansion and compression of vectors ⓘ floating-point vector operations ⓘ fused multiply-add ⓘ gather operations ⓘ integer vector operations ⓘ mask registers ⓘ mask-based blending ⓘ per-lane predication ⓘ permutation instructions ⓘ scatter operations ⓘ vector operations ⓘ vector reductions ⓘ
targetUseCase	data analytics ⓘ high-performance computing ⓘ machine learning workloads ⓘ scientific computing ⓘ signal processing ⓘ
usedIn	Intel Core X-series processors NERFINISHED ⓘ Intel Xeon Scalable processors NERFINISHED ⓘ some Intel client CPUs ⓘ
usesRegisterType	XMM registers ⓘ YMM registers ⓘ ZMM registers ⓘ opmask registers ⓘ

Referenced by (6)

Full triples — surface form annotated when it differs from this entity's canonical label.

x86 → hasExtension → AVX-512 ⓘ

Intel Fortran Compiler → optimizedFor → AVX-512 ⓘ

this entity surface form: Intel AVX-512 instruction set

Intel AVX2 → precedes → AVX-512 ⓘ

this entity surface form: Intel AVX-512

Intel AVX → relatedStandard → AVX-512 ⓘ

this entity surface form: Intel AVX-512

Intel AVX → successor → AVX-512 ⓘ

this entity surface form: Intel AVX-512

Tiger Lake microarchitecture → supports → AVX-512 ⓘ

subject surface form: Tiger Lake