AVX-512
E640424
AVX-512 is an advanced SIMD instruction set for x86 processors that enables high-throughput parallel processing using 512-bit wide vector operations.
All labels observed (3)
| Label | Occurrences |
|---|---|
| Intel AVX-512 | 3 |
| AVX-512 canonical | 2 |
| Intel AVX-512 instruction set | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T7079124 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: AVX-512 Context triple: [x86, hasExtension, AVX-512]
-
A.
Intel AVX2
Intel AVX2 is an x86 instruction set extension from Intel that enhances performance for integer-heavy and vectorized workloads through wider SIMD operations and new vector instructions.
-
B.
Intel AVX
Intel AVX is an x86 processor instruction set extension from Intel that accelerates floating-point and vector-intensive workloads, commonly used in high-performance computing, multimedia, and scientific applications.
-
C.
V (vector extension)
V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
-
D.
AMD-V
AMD-V is AMD’s hardware-assisted virtualization technology that enables efficient and secure running of virtual machines on compatible processors.
-
E.
P (packed-SIMD extension)
P (packed-SIMD extension) is a RISC-V instruction set extension that adds packed single-instruction multiple-data operations to accelerate parallel data processing tasks such as signal processing and multimedia workloads.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: AVX-512 Target entity description: AVX-512 is an advanced SIMD instruction set for x86 processors that enables high-throughput parallel processing using 512-bit wide vector operations.
-
A.
Intel AVX2
Intel AVX2 is an x86 instruction set extension from Intel that enhances performance for integer-heavy and vectorized workloads through wider SIMD operations and new vector instructions.
-
B.
Intel AVX
Intel AVX is an x86 processor instruction set extension from Intel that accelerates floating-point and vector-intensive workloads, commonly used in high-performance computing, multimedia, and scientific applications.
-
C.
V (vector extension)
V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
-
D.
AMD-V
AMD-V is AMD’s hardware-assisted virtualization technology that enables efficient and secure running of virtual machines on compatible processors.
-
E.
P (packed-SIMD extension)
P (packed-SIMD extension) is a RISC-V instruction set extension that adds packed single-instruction multiple-data operations to accelerate parallel data processing tasks such as signal processing and multimedia workloads.
- F. None of above. chosen
Statements (72)
| Predicate | Object |
|---|---|
| instanceOf |
SIMD instruction set
ⓘ
vector instruction set ⓘ |
| architectureFamily | x86 NERFINISHED ⓘ |
| backwardCompatibleWith | AVX2 at instruction-set level ⓘ |
| bitWidth | 512-bit ⓘ |
| comparedTo | AVX2 NERFINISHED ⓘ |
| detectableVia | CPUID instruction ⓘ |
| enables |
high-throughput parallel processing
ⓘ
processing of 16 32-bit integers per vector ⓘ processing of 16 single-precision floats per vector ⓘ processing of 32 16-bit integers per vector ⓘ processing of 64 8-bit integers per vector ⓘ processing of 8 64-bit integers per vector ⓘ processing of 8 double-precision floats per vector ⓘ |
| extends |
AVX
NERFINISHED
ⓘ
AVX2 NERFINISHED ⓘ SSE NERFINISHED ⓘ |
| firstIntroducedInMicroarchitecture |
Intel Knights Landing
NERFINISHED
ⓘ
Intel Skylake-X NERFINISHED ⓘ |
| introducedBy | Intel NERFINISHED ⓘ |
| mayBeDisabledBy | BIOS settings ⓘ |
| mayBeDisabledBy | microcode updates ⓘ |
| opmaskRegisterCount | 8 ⓘ |
| opmaskRegisterWidth | 64-bit ⓘ |
| optimizationConcern |
higher power consumption
ⓘ
thermal throttling risk ⓘ |
| provides |
mask-based predication not in AVX2
ⓘ
more registers than AVX2 ⓘ wider vectors than AVX2 ⓘ |
| registerWidth | 512-bit ZMM registers ⓘ |
| requires | hardware support in CPU ⓘ |
| subset |
AVX-5124FMAPS
NERFINISHED
ⓘ
AVX-5124VNNIW ⓘ AVX-512BF16 NERFINISHED ⓘ AVX-512BITALG NERFINISHED ⓘ AVX-512BW ⓘ AVX-512DQ ⓘ AVX-512ER NERFINISHED ⓘ AVX-512F NERFINISHED ⓘ AVX-512IFMA NERFINISHED ⓘ AVX-512PF NERFINISHED ⓘ AVX-512VBMI NERFINISHED ⓘ AVX-512VL NERFINISHED ⓘ AVX-512VNNI NERFINISHED ⓘ AVX-512VP2INTERSECT ⓘ |
| subset | AVX-512CD NERFINISHED ⓘ |
| supports |
bitwise operations
ⓘ
conflict detection instructions ⓘ expansion and compression of vectors ⓘ floating-point vector operations ⓘ fused multiply-add ⓘ gather operations ⓘ integer vector operations ⓘ mask registers ⓘ mask-based blending ⓘ per-lane predication ⓘ permutation instructions ⓘ scatter operations ⓘ vector operations ⓘ vector reductions ⓘ |
| targetUseCase |
data analytics
ⓘ
high-performance computing ⓘ machine learning workloads ⓘ scientific computing ⓘ signal processing ⓘ |
| usedIn |
Intel Core X-series processors
NERFINISHED
ⓘ
Intel Xeon Scalable processors NERFINISHED ⓘ some Intel client CPUs ⓘ |
| usesRegisterType |
XMM registers
ⓘ
YMM registers ⓘ ZMM registers ⓘ opmask registers ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: AVX-512 Description of subject: AVX-512 is an advanced SIMD instruction set for x86 processors that enables high-throughput parallel processing using 512-bit wide vector operations.
Referenced by (6)
Full triples — surface form annotated when it differs from this entity's canonical label.
this entity surface form:
Intel AVX-512
this entity surface form:
Intel AVX-512
subject surface form:
Tiger Lake
this entity surface form:
Intel AVX-512 instruction set