Triple
T7079124
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | x86 |
E164898
|
entity |
| Predicate | hasExtension |
P455
|
FINISHED |
| Object |
AVX-512
AVX-512 is an advanced SIMD instruction set for x86 processors that enables high-throughput parallel processing using 512-bit wide vector operations.
|
E640424
|
NE FINISHED |
How this triple was built (4 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: AVX-512 | Statement: [x86, hasExtension, AVX-512]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: AVX-512 Context triple: [x86, hasExtension, AVX-512]
-
A.
Intel AVX2
Intel AVX2 is an x86 instruction set extension from Intel that enhances performance for integer-heavy and vectorized workloads through wider SIMD operations and new vector instructions.
-
B.
Intel AVX
Intel AVX is an x86 processor instruction set extension from Intel that accelerates floating-point and vector-intensive workloads, commonly used in high-performance computing, multimedia, and scientific applications.
-
C.
V (vector extension)
V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
-
D.
AMD-V
AMD-V is AMD’s hardware-assisted virtualization technology that enables efficient and secure running of virtual machines on compatible processors.
-
E.
P (packed-SIMD extension)
P (packed-SIMD extension) is a RISC-V instruction set extension that adds packed single-instruction multiple-data operations to accelerate parallel data processing tasks such as signal processing and multimedia workloads.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg
Description generation
gpt-5.1
Instruction
Generate a one-sentence description of the target entity. You are given a context triple in the form (subject, predicate, object), where the object is the target entity. # Instructions Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. Avoid repeating the information from the triple, unless really essential. # Response Format Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: AVX-512 Triple: [x86, hasExtension, AVX-512]
Generated description
AVX-512 is an advanced SIMD instruction set for x86 processors that enables high-throughput parallel processing using 512-bit wide vector operations.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: AVX-512 Target entity description: AVX-512 is an advanced SIMD instruction set for x86 processors that enables high-throughput parallel processing using 512-bit wide vector operations.
-
A.
Intel AVX2
Intel AVX2 is an x86 instruction set extension from Intel that enhances performance for integer-heavy and vectorized workloads through wider SIMD operations and new vector instructions.
-
B.
Intel AVX
Intel AVX is an x86 processor instruction set extension from Intel that accelerates floating-point and vector-intensive workloads, commonly used in high-performance computing, multimedia, and scientific applications.
-
C.
V (vector extension)
V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.
-
D.
AMD-V
AMD-V is AMD’s hardware-assisted virtualization technology that enables efficient and secure running of virtual machines on compatible processors.
-
E.
P (packed-SIMD extension)
P (packed-SIMD extension) is a RISC-V instruction set extension that adds packed single-instruction multiple-data operations to accelerate parallel data processing tasks such as signal processing and multimedia workloads.
- F. None of above. chosen
Provenance (5 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69c6887cbc6c8190bdfac42d940f4d8a |
completed | March 27, 2026, 1:39 p.m. |
| NER | Named-entity recognition | batch_69c6e4ef47d48190b31125d1b57f7bec |
completed | March 27, 2026, 8:13 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69c7947294d4819094d7cfb34efde915 |
completed | March 28, 2026, 8:42 a.m. |
| NEDg | Description generation | batch_69c7954ee22c8190a531e30e8e54f7d5 |
completed | March 28, 2026, 8:46 a.m. |
| NED2 | Entity disambiguation (via description) | batch_69c795fce734819086e20a916aa67f54 |
completed | March 28, 2026, 8:49 a.m. |
Created at: March 27, 2026, 2:40 p.m.