Disambiguation evidence for CPLDs via surface form
"CPLD"
As subject (63)
Triples where this entity appears as subject under the
label "CPLD".
| Predicate | Object |
|---|---|
| canImplement | counters ⓘ |
| canImplement | encoders and decoders ⓘ |
| canImplement | multiplexers and demultiplexers ⓘ |
| canImplement | simple communication protocols ⓘ |
| canImplement | timers ⓘ |
| comparedTo | FPGA ⓘ |
| configurationStorageTechnology | EEPROM ⓘ |
| configurationStorageTechnology | Flash ⓘ |
| configurationStorageTechnology | SRAM with external non-volatile memory in some designs ⓘ |
| configuredBy | JEDEC programming files ⓘ |
| configuredBy | VHDL ⓘ |
| configuredBy | Verilog ⓘ |
| configuredBy | hardware description languages ⓘ |
| configuredBy | vendor-specific schematic entry tools ⓘ |
| developedFrom | GAL devices ⓘ |
| developedFrom | PAL devices ⓘ |
| fullName |
CPLDs
self-linksurface differs
ⓘ
surface form:
Complex Programmable Logic Device
|
| hasAdvantageOverFPGA | often non-volatile configuration ⓘ |
| hasAdvantageOverFPGA | shorter configuration time ⓘ |
| hasAdvantageOverFPGA | simpler architecture ⓘ |
| hasArchitecture | array of macrocells ⓘ |
| hasArchitecture | programmable interconnect matrix ⓘ |
| hasArchitecture | sum-of-products logic structure ⓘ |
| hasComponent | I/O blocks ⓘ |
| hasComponent | fixed or partially programmable OR array ⓘ |
| hasComponent | macrocells with flip-flops ⓘ |
| hasComponent | programmable AND array ⓘ |
| hasDisadvantageComparedToFPGA | less flexible routing resources ⓘ |
| hasDisadvantageComparedToFPGA | lower logic density ⓘ |
| hasProperty | deterministic propagation delay ⓘ |
| hasProperty | fast power-up configuration ⓘ |
| hasProperty | low to moderate power consumption ⓘ |
| hasProperty | non-volatile configuration memory in many families ⓘ |
| hasProperty | predictable timing ⓘ |
| hasProperty | reconfigurable ⓘ |
| hasProperty | relatively low logic capacity compared to FPGAs ⓘ |
| instanceOf | digital integrated circuit ⓘ |
| instanceOf | programmable logic device ⓘ |
| majorVendor | Altera ⓘ |
| majorVendor | Lattice Semiconductor ⓘ |
| majorVendor | Microchip Technology ⓘ |
| majorVendor | Xilinx ⓘ |
| programmedWith | JTAG interface ⓘ |
| programmedWith | in-system programming tools ⓘ |
| supportsFeature | asynchronous and synchronous resets ⓘ |
| supportsFeature | global clock networks ⓘ |
| supportsFeature | registered and combinational outputs ⓘ |
| supportsFeature | tri-state I/O control ⓘ |
| typicalLogicCapacity | tens to a few thousand logic gates ⓘ |
| usedFor | address decoding ⓘ |
| usedFor | bus interfacing ⓘ |
| usedFor | control logic applications ⓘ |
| usedFor | glue logic applications ⓘ |
| usedFor | implementing custom digital logic functions in hardware ⓘ |
| usedFor | interface logic applications ⓘ |
| usedFor | simple digital signal processing control ⓘ |
| usedFor | state machine implementation ⓘ |
| usedIn | automotive electronics ⓘ |
| usedIn | consumer electronics ⓘ |
| usedIn | embedded systems ⓘ |
| usedIn | industrial control systems ⓘ |
| usedIn | prototyping of digital circuits ⓘ |
| usedIn | telecommunications equipment ⓘ |
As object (1)
Triples where some other subject referred to this entity
as "CPLD".