Triple
T2088706
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Moore's law |
E32615
|
entity |
| Predicate | originalArticleTitle |
P6930
|
FINISHED |
| Object | Cramming more components onto integrated circuits |
E32616
|
NE FINISHED |
How this triple was built (3 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Cramming more components onto integrated circuits | Statement: [Moore's law, originalArticleTitle, Cramming more components onto integrated circuits]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: Cramming more components onto integrated circuits Context triple: [Moore's law, originalArticleTitle, Cramming more components onto integrated circuits]
-
A.
“Cramming more components onto integrated circuits”
chosen
“Cramming more components onto integrated circuits” is the landmark 1965 article by Gordon E. Moore that introduced the observation later known as Moore’s Law, predicting the exponential growth of transistor density on integrated circuits.
-
B.
Microprocessor without Interlocked Pipeline Stages
Microprocessor without Interlocked Pipeline Stages (MIPS) is a RISC microprocessor architecture known for its simple, efficient design and widespread use in embedded systems, workstations, and educational settings.
-
C.
Moore's law
Moore's law is an observation and prediction that the number of transistors on an integrated circuit—and thus computing power—tends to roughly double at regular intervals, driving exponential growth in digital technology.
-
D.
VLSI technology
VLSI technology (Very Large Scale Integration) is the process of creating integrated circuits by combining thousands to millions of transistors on a single chip, enabling complex and high-performance electronic systems.
-
E.
Xe-HPG microarchitecture
Xe-HPG microarchitecture is Intel’s high-performance gaming-oriented GPU architecture designed to power its discrete Arc graphics cards with advanced features like hardware-accelerated ray tracing.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
PD
Predicate disambiguation
gpt-5-mini-2025-08-07
Target predicate: originalArticleTitle Context triple: [Moore's law, originalArticleTitle, Cramming more components onto integrated circuits]
-
A.
originalTitleOfWork
chosen
Indicates that one work is the original title under which another work was first created, published, or released.
-
B.
publicationTitle
Indicates the name or title under which a work (such as an article, book, or paper) is formally published.
-
C.
originallyTitleOf
Indicates that one title is the original title from which another work, edition, or localized title is derived.
-
D.
originalText
Indicates that one text is the initial, unmodified version from which other versions, translations, or representations are derived.
-
E.
originalLanguageTitle
Indicates the title of a work as it appears in its original language of creation or publication.
- F. None of above.
Provenance (4 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69a885eba0708190999696a45cbec816 |
completed | March 4, 2026, 7:20 p.m. |
| NER | Named-entity recognition | batch_69abba712388819091d68a4bb99f6b17 |
completed | March 7, 2026, 5:41 a.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69ae2742834c8190ad9be71128959e0c |
completed | March 9, 2026, 1:49 a.m. |
| PD | Predicate disambiguation | batch_69abb7b4356881909217c42ccb8bb1ed |
completed | March 7, 2026, 5:29 a.m. |
Created at: March 4, 2026, 7:43 p.m.