Triple

T11804170
Position Surface form Disambiguated ID Type / Status
Subject IEEE 1149.10 E280701 entity
Predicate relatedTo P37 FINISHED
Object JTAG E1466 NE FINISHED

How this triple was built (2 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: JTAG | Statement: [IEEE 1149.10, relatedTo, JTAG]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07 
Target entity: JTAG
Context triple: [IEEE 1149.10, relatedTo, JTAG]
  • A. IEEE 1149.1 JTAG boundary‑scan standard chosen
    The IEEE 1149.1 JTAG boundary-scan standard is a widely used test and debug specification that defines a serial interface and architecture for accessing and testing the internal logic and interconnects of integrated circuits and circuit boards.
  • B. IEEE 1149.6
    IEEE 1149.6 is a boundary-scan test standard that extends JTAG to support structural testing of high-speed AC-coupled and differential digital interconnects on printed circuit boards.
  • C. IEEE 1149.4
    IEEE 1149.4 is a mixed-signal test bus standard that extends JTAG boundary-scan techniques to support testing and diagnosis of analog and mixed-signal circuits on printed circuit boards.
  • D. IEEE 1149.7
    IEEE 1149.7 is a compact, enhanced version of the JTAG test and debug standard that reduces pin count and power while adding advanced debug and trace capabilities for modern integrated circuits.
  • E. IEEE Standard for High-Speed Test Access Port and Boundary-Scan Architecture
    IEEE 1149.10 is a JTAG-related IEEE standard that defines a high-speed test access and boundary-scan architecture for efficient testing and debugging of complex digital integrated circuits and systems.
  • F. None of above.
  • G. Unsure - the case is ambiguous/there is not enough information to decide.

Provenance (3 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69d6ab26aae88190b2489efcb2a24234 completed April 8, 2026, 7:23 p.m.
NER Named-entity recognition batch_69d8a5a5a2048190b68027f622366079 completed April 10, 2026, 7:24 a.m.
NED1 Entity disambiguation (via context triple) batch_69f1314300248190847b9c61bbfda121 completed April 28, 2026, 10:14 p.m.
Created at: April 8, 2026, 9:42 p.m.