POWER4
E758592
POWER4 is a 64-bit microprocessor developed by IBM that introduced a dual-core design and high-performance server capabilities in the early 2000s.
All labels observed (1)
| Label | Occurrences |
|---|---|
| POWER4 canonical | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T8814735 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: POWER4 Context triple: [POWER3, successor, POWER4]
-
A.
POWER1
POWER1 is IBM’s first-generation 32-bit RISC microprocessor architecture used in early RS/6000 workstations and servers.
-
B.
POWER2
POWER2 is a second-generation IBM RISC microprocessor architecture designed to deliver high-performance computing, particularly for scientific and technical workloads.
-
C.
PWR
PWR is a global interfaith organization that convenes leaders and followers of diverse religious and spiritual traditions to promote dialogue, understanding, and cooperation for peace and justice.
-
D.
POWER3
POWER3 is a 64-bit RISC microprocessor from IBM’s POWER architecture line, designed for high-performance technical and scientific computing systems.
-
E.
PWRR
PWRR is a line infantry regiment of the British Army, known as the Princess of Wales's Royal Regiment.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: POWER4 Target entity description: POWER4 is a 64-bit microprocessor developed by IBM that introduced a dual-core design and high-performance server capabilities in the early 2000s.
-
A.
POWER1
POWER1 is IBM’s first-generation 32-bit RISC microprocessor architecture used in early RS/6000 workstations and servers.
-
B.
POWER2
POWER2 is a second-generation IBM RISC microprocessor architecture designed to deliver high-performance computing, particularly for scientific and technical workloads.
-
C.
PWR
PWR is a global interfaith organization that convenes leaders and followers of diverse religious and spiritual traditions to promote dialogue, understanding, and cooperation for peace and justice.
-
D.
POWER3
POWER3 is a 64-bit RISC microprocessor from IBM’s POWER architecture line, designed for high-performance technical and scientific computing systems.
-
E.
PWRR
PWRR is a line infantry regiment of the British Army, known as the Princess of Wales's Royal Regiment.
- F. None of above. chosen
Statements (48)
| Predicate | Object |
|---|---|
| instanceOf |
64-bit microprocessor
ⓘ
IBM POWER architecture processor ⓘ microprocessor ⓘ |
| alsoKnownAs | IBM POWER4 NERFINISHED ⓘ |
| architecture | POWER NERFINISHED ⓘ |
| cacheHierarchy |
off-chip L3 cache support
ⓘ
on-chip L1 cache ⓘ on-chip L2 cache ⓘ |
| category | server processor ⓘ |
| company | IBM NERFINISHED ⓘ |
| companyPlatform | IBM eServer pSeries NERFINISHED ⓘ |
| coreCount | 2 ⓘ |
| design | dual-core ⓘ |
| developer | IBM ⓘ |
| dieIntegration | two processor cores on a single die ⓘ |
| endianness | big-endian ⓘ |
| executionType | out-of-order execution ⓘ |
| fabricationTechnology | CMOS ⓘ |
| family | IBM POWER family NERFINISHED ⓘ |
| floatingPointUnit | integrated high-performance FPU ⓘ |
| generation | fourth-generation POWER processor ⓘ |
| instructionSetArchitecture | PowerPC NERFINISHED ⓘ |
| introductionYear | 2001 ⓘ |
| L1CacheType | separate instruction and data caches ⓘ |
| marketPosition | high-end RISC server CPU ⓘ |
| microarchitecture | POWER4 microarchitecture NERFINISHED ⓘ |
| notableFeature |
first commercially available dual-core POWER processor from IBM
ⓘ
highly integrated chip with two cores and large shared cache ⓘ |
| operatingSystems |
AIX
NERFINISHED
ⓘ
Linux on Power NERFINISHED ⓘ |
| pipelineType | superscalar ⓘ |
| powerManagement | server-optimized power and thermal design ⓘ |
| predecessor | POWER3 NERFINISHED ⓘ |
| primaryUse |
high-performance computing
ⓘ
servers ⓘ |
| registerArchitecture | general-purpose registers and floating-point registers per POWER/PowerPC spec ⓘ |
| successor | POWER5 NERFINISHED ⓘ |
| supports |
64-bit floating-point operations
ⓘ
64-bit integer operations ⓘ RISC (reduced instruction set computing) principles ⓘ simultaneous multithreading disabled (single-threaded per core) ⓘ |
| targetMarket |
UNIX servers
ⓘ
enterprise servers ⓘ |
| technologyNode | 130 nm-class process (approximate) ⓘ |
| usedIn |
IBM RS/6000 servers
NERFINISHED
ⓘ
IBM pSeries servers NERFINISHED ⓘ |
| vendor | IBM Microelectronics NERFINISHED ⓘ |
| wordSize | 64-bit ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: POWER4 Description of subject: POWER4 is a 64-bit microprocessor developed by IBM that introduced a dual-core design and high-performance server capabilities in the early 2000s.
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.