POWER4
E758592
POWER4 is a 64-bit microprocessor developed by IBM that introduced a dual-core design and high-performance server capabilities in the early 2000s.
Statements (48)
| Predicate | Object |
|---|---|
| instanceOf |
64-bit microprocessor
ⓘ
IBM POWER architecture processor ⓘ microprocessor ⓘ |
| alsoKnownAs | IBM POWER4 NERFINISHED ⓘ |
| architecture | POWER NERFINISHED ⓘ |
| cacheHierarchy |
off-chip L3 cache support
ⓘ
on-chip L1 cache ⓘ on-chip L2 cache ⓘ |
| category | server processor ⓘ |
| company | IBM NERFINISHED ⓘ |
| companyPlatform | IBM eServer pSeries NERFINISHED ⓘ |
| coreCount | 2 ⓘ |
| design | dual-core ⓘ |
| developer | IBM ⓘ |
| dieIntegration | two processor cores on a single die ⓘ |
| endianness | big-endian ⓘ |
| executionType | out-of-order execution ⓘ |
| fabricationTechnology | CMOS ⓘ |
| family | IBM POWER family NERFINISHED ⓘ |
| floatingPointUnit | integrated high-performance FPU ⓘ |
| generation | fourth-generation POWER processor ⓘ |
| instructionSetArchitecture | PowerPC NERFINISHED ⓘ |
| introductionYear | 2001 ⓘ |
| L1CacheType | separate instruction and data caches ⓘ |
| marketPosition | high-end RISC server CPU ⓘ |
| microarchitecture | POWER4 microarchitecture NERFINISHED ⓘ |
| notableFeature |
first commercially available dual-core POWER processor from IBM
ⓘ
highly integrated chip with two cores and large shared cache ⓘ |
| operatingSystems |
AIX
NERFINISHED
ⓘ
Linux on Power NERFINISHED ⓘ |
| pipelineType | superscalar ⓘ |
| powerManagement | server-optimized power and thermal design ⓘ |
| predecessor | POWER3 NERFINISHED ⓘ |
| primaryUse |
high-performance computing
ⓘ
servers ⓘ |
| registerArchitecture | general-purpose registers and floating-point registers per POWER/PowerPC spec ⓘ |
| successor | POWER5 NERFINISHED ⓘ |
| supports |
64-bit floating-point operations
ⓘ
64-bit integer operations ⓘ RISC (reduced instruction set computing) principles ⓘ simultaneous multithreading disabled (single-threaded per core) ⓘ |
| targetMarket |
UNIX servers
ⓘ
enterprise servers ⓘ |
| technologyNode | 130 nm-class process (approximate) ⓘ |
| usedIn |
IBM RS/6000 servers
NERFINISHED
ⓘ
IBM pSeries servers NERFINISHED ⓘ |
| vendor | IBM Microelectronics NERFINISHED ⓘ |
| wordSize | 64-bit ⓘ |
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.