L1CacheType
P158297
predicate
Indicates the specific configuration or design category of a system’s Level 1 cache in relation to how it stores and accesses data or instructions.
Observed surface forms (1)
- L1CacheSplit ×4
Sample triples (10)
| Subject | Object |
|---|---|
| Duron | 64 KB data cache via predicate surface "L1CacheSplit" ⓘ |
| Duron | 64 KB instruction cache via predicate surface "L1CacheSplit" ⓘ |
| Intel Pentium 133 | 8 KB data cache via predicate surface "L1CacheSplit" ⓘ |
| Intel Pentium 133 | 8 KB instruction cache via predicate surface "L1CacheSplit" ⓘ |
| Intel Pentium II | split instruction and data cache ⓘ |
| McKinley | separate instruction and data caches ⓘ |
| POWER4 | separate instruction and data caches ⓘ |
| Paris | split instruction and data cache ⓘ |
| Prescott | trace cache for instructions ⓘ |
| Sparta | split instruction and data cache ⓘ |