MIPS V
E729283
MIPS V is a later revision of the MIPS instruction set architecture that extends earlier versions with enhanced support for 64-bit operations and improved performance features.
All labels observed (1)
| Label | Occurrences |
|---|---|
| MIPS V canonical | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T8284550 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: MIPS V Context triple: [Microprocessor without Interlocked Pipeline Stages, hasVariant, MIPS V]
-
A.
MIPS IV
MIPS IV is a 64-bit RISC instruction set architecture in the MIPS family, designed to enhance performance and support advanced computing features over its predecessors.
-
B.
MIPS II
MIPS II is the second-generation version of the MIPS instruction set architecture, extending the original design with additional instructions and features for improved performance and functionality.
-
C.
MIPS III
MIPS III is a 64-bit RISC instruction set architecture in the MIPS family, extending earlier versions with larger address space and enhanced computational capabilities.
-
D.
MIPS R5000
The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
E.
MIPS R4600
The MIPS R4600 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: MIPS V Target entity description: MIPS V is a later revision of the MIPS instruction set architecture that extends earlier versions with enhanced support for 64-bit operations and improved performance features.
-
A.
MIPS IV
MIPS IV is a 64-bit RISC instruction set architecture in the MIPS family, designed to enhance performance and support advanced computing features over its predecessors.
-
B.
MIPS II
MIPS II is the second-generation version of the MIPS instruction set architecture, extending the original design with additional instructions and features for improved performance and functionality.
-
C.
MIPS III
MIPS III is a 64-bit RISC instruction set architecture in the MIPS family, extending earlier versions with larger address space and enhanced computational capabilities.
-
D.
MIPS R5000
The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
E.
MIPS R4600
The MIPS R4600 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
- F. None of above. chosen
Statements (25)
| Predicate | Object |
|---|---|
| instanceOf |
MIPS architecture revision
ⓘ
instruction set architecture ⓘ |
| architectureStyle | RISC NERFINISHED ⓘ |
| belongsTo | MIPS ISA versions ⓘ |
| compatibleWith | earlier MIPS revisions (to a large extent) ⓘ |
| designedBy | MIPS Technologies NERFINISHED ⓘ |
| designedFor | 64-bit operations ⓘ |
| extends | MIPS IV NERFINISHED ⓘ |
| follows | MIPS IV NERFINISHED ⓘ |
| hasDesignGoal |
efficient 64-bit computation
ⓘ
higher performance than MIPS IV ⓘ |
| hasFeature |
additional instructions over MIPS IV
ⓘ
enhanced 64-bit support ⓘ improved performance features ⓘ |
| hasProperty |
fixed-length instructions
ⓘ
load-store architecture ⓘ register-based operations ⓘ |
| partOf | MIPS architecture family ⓘ |
| precedes | later MIPS revisions (such as MIPS32 and MIPS64 families) ⓘ |
| supports |
64-bit floating-point operations
ⓘ
64-bit integer operations ⓘ |
| targetDomain |
embedded systems
ⓘ
general-purpose computing ⓘ |
| usedIn | 64-bit MIPS processors ⓘ |
| wordSize | 64-bit ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: MIPS V Description of subject: MIPS V is a later revision of the MIPS instruction set architecture that extends earlier versions with enhanced support for 64-bit operations and improved performance features.
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.