MIPS V
E729283
MIPS V is a later revision of the MIPS instruction set architecture that extends earlier versions with enhanced support for 64-bit operations and improved performance features.
All labels observed (1)
| Label | Occurrences |
|---|---|
| MIPS V canonical | 1 |
Statements (25)
| Predicate | Object |
|---|---|
| instanceOf |
MIPS architecture revision
ⓘ
instruction set architecture ⓘ |
| architectureStyle | RISC NERFINISHED ⓘ |
| belongsTo | MIPS ISA versions ⓘ |
| compatibleWith | earlier MIPS revisions (to a large extent) ⓘ |
| designedBy | MIPS Technologies NERFINISHED ⓘ |
| designedFor | 64-bit operations ⓘ |
| extends | MIPS IV NERFINISHED ⓘ |
| follows | MIPS IV NERFINISHED ⓘ |
| hasDesignGoal |
efficient 64-bit computation
ⓘ
higher performance than MIPS IV ⓘ |
| hasFeature |
additional instructions over MIPS IV
ⓘ
enhanced 64-bit support ⓘ improved performance features ⓘ |
| hasProperty |
fixed-length instructions
ⓘ
load-store architecture ⓘ register-based operations ⓘ |
| partOf | MIPS architecture family ⓘ |
| precedes | later MIPS revisions (such as MIPS32 and MIPS64 families) ⓘ |
| supports |
64-bit floating-point operations
ⓘ
64-bit integer operations ⓘ |
| targetDomain |
embedded systems
ⓘ
general-purpose computing ⓘ |
| usedIn | 64-bit MIPS processors ⓘ |
| wordSize | 64-bit ⓘ |
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.