Triple
T8284550
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Microprocessor without Interlocked Pipeline Stages |
E193757
|
entity |
| Predicate | hasVariant |
P455
|
FINISHED |
| Object |
MIPS V
MIPS V is a later revision of the MIPS instruction set architecture that extends earlier versions with enhanced support for 64-bit operations and improved performance features.
|
E729283
|
NE FINISHED |
Provenance (5 batches)
| Stage | Batch ID | Job type | Status |
|---|---|---|---|
| creating | batch_69ca82e217a48190880695635c44b2ed |
elicitation | completed |
| NER | batch_69cb7ad0535081908bb234cfc0e32b32 |
ner | completed |
| NED1 | batch_69cde76537108190a1e1f92b97432698 |
ned_source_triple | completed |
| NED2 | batch_69cdec3081d88190ad0699f9072d3fc7 |
ned_description | completed |
| NEDg | batch_69cdeb1fa7308190810b1fcc2184374a |
nedg | completed |
Created at: March 30, 2026, 5:52 p.m.