OpenRISC
E724163
OpenRISC is an open-source RISC processor architecture designed for flexibility, research, and embedded systems development.
Statements (48)
| Predicate | Object |
|---|---|
| instanceOf |
RISC instruction set architecture
ⓘ
open hardware project ⓘ open-source processor architecture ⓘ |
| architectureType | RISC ⓘ |
| category |
embedded microprocessors
ⓘ
instruction set architectures ⓘ open-source hardware ⓘ |
| designGoal |
flexibility
ⓘ
portability ⓘ simplicity ⓘ |
| developer | OpenCores community ⓘ |
| ecosystem |
FPGA reference designs
ⓘ
Linux kernel port ⓘ QEMU target ⓘ SoC reference platforms ⓘ newlib support ⓘ uClibc support ⓘ |
| feature |
32 general-purpose registers (in common implementations)
ⓘ
debug interface ⓘ exceptions support ⓘ interrupt support ⓘ load-store architecture ⓘ orthogonal instruction set ⓘ support for caches (in some cores) ⓘ support for hardware multiply and divide (in some cores) ⓘ |
| hasImplementation |
OR10 core
NERFINISHED
ⓘ
OR1200 Verilog implementation NERFINISHED ⓘ OR1200 core NERFINISHED ⓘ OR1K architecture NERFINISHED ⓘ |
| hostedAt | OpenCores.org NERFINISHED ⓘ |
| influenced |
development of RISC-V ecosystem awareness
ⓘ
research on open ISAs ⓘ |
| intendedUse |
education
ⓘ
embedded systems ⓘ research ⓘ |
| license | open-source license ⓘ |
| origin | early 2000s ⓘ |
| status | actively used in research and hobbyist projects ⓘ |
| supports |
32-bit implementations
ⓘ
Harvard architecture implementations ⓘ Linux NERFINISHED ⓘ MMU-based operating systems ⓘ uClinux NERFINISHED ⓘ virtual memory ⓘ |
| toolchain |
GCC
NERFINISHED
ⓘ
GDB NERFINISHED ⓘ LLVM (partial support) ⓘ binutils NERFINISHED ⓘ |
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.