Triple

T8285572
Position Surface form Disambiguated ID Type / Status
Subject QEMU E193779 entity
Predicate supportsGuestArchitecture P82507 FINISHED
Object OpenRISC
OpenRISC is an open-source RISC processor architecture designed for flexibility, research, and embedded systems development.
 E724163 NE FINISHED

How this triple was built (4 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: OpenRISC | Statement: [QEMU, supportsGuestArchitecture, OpenRISC]
NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07 
Target entity: OpenRISC
Context triple: [QEMU, supportsGuestArchitecture, OpenRISC]
  • A. RISC-V
    RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
  • B. Acorn RISC Machine
    Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
  • C. Spike RISC-V ISA simulator
    Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
  • D. AROS Research Operating System
    AROS Research Operating System is an open-source, portable reimplementation of the classic AmigaOS designed to run on modern hardware and architectures.
  • E. Risc PC
    Risc PC is a modular personal computer introduced by Acorn Computers in the 1990s, known for its RISC-based architecture and expandability.
  • F. None of above. chosen
  • G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg Description generation gpt-5.1
Instruction
Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: OpenRISC
Triple: [QEMU, supportsGuestArchitecture, OpenRISC]
Generated description
OpenRISC is an open-source RISC processor architecture designed for flexibility, research, and embedded systems development.
NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07 
Target entity: OpenRISC
Target entity description: OpenRISC is an open-source RISC processor architecture designed for flexibility, research, and embedded systems development.
  • A. RISC-V
    RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
  • B. Acorn RISC Machine
    Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
  • C. Spike RISC-V ISA simulator
    Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
  • D. AROS Research Operating System
    AROS Research Operating System is an open-source, portable reimplementation of the classic AmigaOS designed to run on modern hardware and architectures.
  • E. Risc PC
    Risc PC is a modular personal computer introduced by Acorn Computers in the 1990s, known for its RISC-based architecture and expandability.
  • F. None of above. chosen

Provenance (5 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69ca82e32db481908b72f3804fa71152 completed March 30, 2026, 2:04 p.m.
NER Named-entity recognition batch_69cbd11ed22c819082bf036602eaa038 completed March 31, 2026, 1:50 p.m.
NED1 Entity disambiguation (via context triple) batch_69cd687e64a08190a45a1cf5f5c32291 completed April 1, 2026, 6:48 p.m.
NEDg Description generation batch_69cd6d55196881909cf5ec925792e09f completed April 1, 2026, 7:09 p.m.
NED2 Entity disambiguation (via description) batch_69cd7e2bdae08190adc51e904e85695e completed April 1, 2026, 8:21 p.m.
Created at: March 30, 2026, 5:52 p.m.