MIPS II
E724103
MIPS II is the second-generation version of the MIPS instruction set architecture, extending the original design with additional instructions and features for improved performance and functionality.
All labels observed (1)
| Label | Occurrences |
|---|---|
| MIPS II canonical | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T8284547 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: MIPS II Context triple: [Microprocessor without Interlocked Pipeline Stages, hasVariant, MIPS II]
-
A.
MIPS R5000
The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
B.
MIPS R4600
The MIPS R4600 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
C.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
D.
RISC II
RISC II is an early experimental reduced instruction set computer (RISC) processor developed at UC Berkeley that significantly shaped the design of later RISC architectures.
-
E.
Risc PC
Risc PC is a modular personal computer introduced by Acorn Computers in the 1990s, known for its RISC-based architecture and expandability.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: MIPS II Target entity description: MIPS II is the second-generation version of the MIPS instruction set architecture, extending the original design with additional instructions and features for improved performance and functionality.
-
A.
MIPS R5000
The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
B.
MIPS R4600
The MIPS R4600 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
C.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
D.
RISC II
RISC II is an early experimental reduced instruction set computer (RISC) processor developed at UC Berkeley that significantly shaped the design of later RISC architectures.
-
E.
Risc PC
Risc PC is a modular personal computer introduced by Acorn Computers in the 1990s, known for its RISC-based architecture and expandability.
- F. None of above. chosen
Statements (40)
| Predicate | Object |
|---|---|
| instanceOf |
MIPS architecture revision
ⓘ
instruction set architecture ⓘ |
| addressSize | 32-bit ⓘ |
| addsInstruction |
conditional move instructions
ⓘ
new branch instructions ⓘ new load and store variants ⓘ new trap instructions ⓘ |
| architectureFamily | MIPS NERFINISHED ⓘ |
| compatibleWith | MIPS I binaries ⓘ |
| designedBy | MIPS Computer Systems NERFINISHED ⓘ |
| endianness |
big-endian support
ⓘ
little-endian support ⓘ |
| executionModel | RISC NERFINISHED ⓘ |
| extends | MIPS I instruction set NERFINISHED ⓘ |
| follows | MIPS I NERFINISHED ⓘ |
| hasFeature |
fixed-length 32-bit instructions
ⓘ
separate integer and coprocessor instruction spaces ⓘ support for virtual memory (via TLB in implementations) ⓘ |
| improves |
code density over MIPS I
ⓘ
performance over MIPS I ⓘ |
| numericDesignation | MIPS ISA level II NERFINISHED ⓘ |
| precedes | MIPS III NERFINISHED ⓘ |
| registerCount | 32 general-purpose registers ⓘ |
| standardizedIn | MIPS architecture manuals NERFINISHED ⓘ |
| supports |
branch instructions
ⓘ
coprocessor interface ⓘ delayed branch ⓘ integer operations ⓘ jump instructions ⓘ load and store operations ⓘ load delay slots (in some implementations) ⓘ logical operations ⓘ shift operations ⓘ trap instructions ⓘ |
| usedIn |
embedded systems
ⓘ
workstation-class processors ⓘ |
| usesRegister |
HI register
ⓘ
LO register ⓘ program counter ⓘ |
| wordSize | 32-bit ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: MIPS II Description of subject: MIPS II is the second-generation version of the MIPS instruction set architecture, extending the original design with additional instructions and features for improved performance and functionality.
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.