MIPS II
E724103
MIPS II is the second-generation version of the MIPS instruction set architecture, extending the original design with additional instructions and features for improved performance and functionality.
Statements (40)
| Predicate | Object |
|---|---|
| instanceOf |
MIPS architecture revision
ⓘ
instruction set architecture ⓘ |
| addressSize | 32-bit ⓘ |
| addsInstruction |
conditional move instructions
ⓘ
new branch instructions ⓘ new load and store variants ⓘ new trap instructions ⓘ |
| architectureFamily | MIPS NERFINISHED ⓘ |
| compatibleWith | MIPS I binaries ⓘ |
| designedBy | MIPS Computer Systems NERFINISHED ⓘ |
| endianness |
big-endian support
ⓘ
little-endian support ⓘ |
| executionModel | RISC NERFINISHED ⓘ |
| extends | MIPS I instruction set NERFINISHED ⓘ |
| follows | MIPS I NERFINISHED ⓘ |
| hasFeature |
fixed-length 32-bit instructions
ⓘ
separate integer and coprocessor instruction spaces ⓘ support for virtual memory (via TLB in implementations) ⓘ |
| improves |
code density over MIPS I
ⓘ
performance over MIPS I ⓘ |
| numericDesignation | MIPS ISA level II NERFINISHED ⓘ |
| precedes | MIPS III NERFINISHED ⓘ |
| registerCount | 32 general-purpose registers ⓘ |
| standardizedIn | MIPS architecture manuals NERFINISHED ⓘ |
| supports |
branch instructions
ⓘ
coprocessor interface ⓘ delayed branch ⓘ integer operations ⓘ jump instructions ⓘ load and store operations ⓘ load delay slots (in some implementations) ⓘ logical operations ⓘ shift operations ⓘ trap instructions ⓘ |
| usedIn |
embedded systems
ⓘ
workstation-class processors ⓘ |
| usesRegister |
HI register
ⓘ
LO register ⓘ program counter ⓘ |
| wordSize | 32-bit ⓘ |
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.